[coreboot-gerrit] Patch set updated for coreboot: soc/intel/skylake: Perform early chipset programming

[Subrata Banik (subrata.banik@intel.com)]

Subrata Banik (subrata.banik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15819

-gerrit

commit ff17ce8aaa91aee9d4a7c0c0ce173d00d3e6602a
Author: Subrata Banik <subrata.banik at intel.com>
Date:   Fri Jul 22 21:51:42 2016 +0530

    soc/intel/skylake: Perform early chipset programming
    
    Move PCH programming from verstage to early romstage.
    
    BUG=chrome-os-partner:55357
    BRANCH=none
    TEST=Built and booted kunimitsu
    
    Change-Id: Ie763f3a73e0a76817dd682adfd9fe3c7c11207cf
    Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
    Signed-off-by: Shirish S <shirish.s at intel.com>
    Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
 src/drivers/intel/fsp1_1/include/fsp/romstage.h |  6 ++++
 src/drivers/intel/fsp1_1/romstage.c             |  9 ++++++
 src/soc/intel/skylake/romstage/pch.c            | 38 -------------------------
 src/soc/intel/skylake/romstage/romstage.c       |  2 +-
 4 files changed, 16 insertions(+), 39 deletions(-)

diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
index d07dc37..d3cf818 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
@@ -84,6 +84,12 @@ void *setup_stack_and_mtrrs(void);
 void soc_after_ram_init(struct romstage_params *params);
 void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
 	MEMORY_INIT_UPD *new);
+/*
+ * Perform early chipset initialization before fsp memory init
+ * example: pirq->irq programming, enabling smbus, pmcbase, abase,
+ * 			get platform info, i2c programming
+ */
+void soc_early_pch_init(void);
 void soc_memory_init_params(struct romstage_params *params,
 			    MEMORY_INIT_UPD *upd);
 void soc_pre_ram_init(struct romstage_params *params);
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index c1b1ca5..a98210a 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -38,6 +38,11 @@
 #include <tpm.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
+#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
+/* Perform early chipset initialization before fsp memory init */
+__attribute__((weak)) void soc_early_pch_init(void) { /* no-op */ }
+#endif
+
 asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
 {
 	void *top_of_stack;
@@ -55,6 +60,10 @@ asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
 	if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS))
 		intel_update_microcode_from_cbfs();
 
+	/* Early pch chipset init */
+	if (IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK))
+		soc_early_pch_init();
+
 	memset(&pei_data, 0, sizeof(pei_data));
 
 	/* Display parameters */
diff --git a/src/soc/intel/skylake/romstage/pch.c b/src/soc/intel/skylake/romstage/pch.c
index 1196c5e..ea0bd85 100644
--- a/src/soc/intel/skylake/romstage/pch.c
+++ b/src/soc/intel/skylake/romstage/pch.c
@@ -44,42 +44,6 @@ static const u8 pch_interrupt_routing[] = {
 		11	/* PHRC: PIRQH -> IRQ11 */
 };
 
-static void pch_enable_lpc(void)
-{
-	/* Lookup device tree in romstage */
-	const struct device *dev;
-	const config_t *config;
-	u16 lpc_en;
-
-	/* IO Decode Range */
-	lpc_en = COMA_RANGE | (COMB_RANGE << 4);
-	pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, lpc_en);
-	pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOD, lpc_en);
-
-	/* IO Decode Enable */
-	lpc_en = CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN | GAMEH_LPC_EN |
-		COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN;
-	pci_write_config16(PCH_DEV_LPC, LPC_EN, lpc_en);
-	pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOE, lpc_en);
-
-	dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
-	if (!dev || !dev->chip_info)
-		return;
-	config = dev->chip_info;
-
-	/* Set in PCI generic decode range registers */
-	pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec);
-	pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec);
-	pci_write_config32(PCH_DEV_LPC, LPC_GEN3_DEC, config->gen3_dec);
-	pci_write_config32(PCH_DEV_LPC, LPC_GEN4_DEC, config->gen4_dec);
-
-	/* Mirror these same settings in DMI PCR */
-	pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR1, config->gen1_dec);
-	pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR2, config->gen2_dec);
-	pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR3, config->gen3_dec);
-	pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR4, config->gen4_dec);
-}
-
 static void pch_device_init(void)
 {
 	device_t dev;
@@ -127,7 +91,5 @@ void pch_early_init(void)
 
 	pch_interrupt_init();
 
-	pch_enable_lpc();
-
 	enable_smbus();
 }
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 9f46fd9..ac5d0e9 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -49,7 +49,7 @@ void soc_pre_ram_init(struct romstage_params *params)
 	soc_fill_pei_data(params->pei_data);
 }
 
-void car_soc_post_console_init(void)
+void soc_early_pch_init(void)
 {
 	report_platform_info();
 	set_max_freq();