[coreboot-gerrit] New patch to review for coreboot: nb/intel/x4x: Use older detection scheme for maximum memory frequency

[Damien Zammit (damien@zamaudio.com)]

Damien Zammit (damien at zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15818

-gerrit

commit 190c494454121a86464a3a6597d1fe9019811c45
Author: Damien Zammit <damien at zamaudio.com>
Date:   Sun Jul 24 03:28:42 2016 +1000

    nb/intel/x4x: Use older detection scheme for maximum memory frequency
    
    The current scheme for detecting max memory frequency is flawed.
    Revert to older scheme (which is based on gm45 code).
    Can't do any better since it is undocumented.
    
    Could hardcode to 667 which would work in all cases,
    but 800 would never be used.
    
    This now works on Core2 Quad with 2x2GB(DDR2-800) populated DIMMs running
    at 667MHz, but did not work before at max detected 800MHz.
    
    Change-Id: I1ddd7827ee6fe3d4162ba0546f738a8f9decdf93
    Signed-off-by: Damien Zammit <damien at zamaudio.com>
---
 src/northbridge/intel/x4x/raminit.c | 25 ++++++++-----------------
 1 file changed, 8 insertions(+), 17 deletions(-)

diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 9be2cd3..e607e66 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -264,8 +264,6 @@ static u8 msbpos(u8 val) //Reverse
 
 static void mchinfo_ddr2(struct sysinfo *s)
 {
-	u8 capablefreq, maxfreq;
-
 	const u32 eax = cpuid_ext(0x04, 0).eax;
 	s->cores = ((eax >> 26) & 0x3f) + 1;
 	printk(BIOS_WARNING, "%d CPU cores\n", s->cores);
@@ -284,19 +282,7 @@ static void mchinfo_ddr2(struct sysinfo *s)
 		printk(BIOS_WARNING, "AMT enabled\n");
 	}
 
-	maxfreq = MEM_CLOCK_800MHz;
-	capablefreq = (u8)((pci_read_config16(PCI_DEV(0, 0, 0), 0xea) >> 4) & 0x3f);
-	capablefreq &= 0x7;
-	if (capablefreq)
-		maxfreq = capablefreq + 1;
-
-	if (maxfreq > MEM_CLOCK_800MHz)
-		maxfreq = MEM_CLOCK_800MHz;
-
-	if (maxfreq < MEM_CLOCK_667MHz)
-		maxfreq = MEM_CLOCK_667MHz;
-
-	s->max_ddr2_mhz = (maxfreq == MEM_CLOCK_800MHz) ? 800 : 667;
+	s->max_ddr2_mhz = (capid & (1<<(53-32)))?667:800;
 	printk(BIOS_WARNING, "Capable of DDR2 of %d MHz or lower\n", s->max_ddr2_mhz);
 
 	if (!(capid & (1<<(48-32)))) {
@@ -337,8 +323,13 @@ static void sdram_detect_ram_speed(struct sysinfo *s)
 		// Choose max memory frequency for MCH as previously detected
 		freq = (s->max_ddr2_mhz == 800) ? MEM_CLOCK_800MHz : MEM_CLOCK_667MHz;
 
-		// Detect a common CAS latency (Choose from 6,5,4 CL)
-		commoncas = 0x70;
+		// Detect a common CAS latency
+		// Choose from {6,5,4}@800 or {5,4}@667
+		if (freq == MEM_CLOCK_800MHz) {
+			commoncas = 0x70;
+		} else {
+			commoncas = 0x30;
+		}
 		FOR_EACH_POPULATED_DIMM(s->dimms, i) {
 			commoncas &= s->dimms[i].cas_latencies;
 		}