[coreboot-gerrit] Patch merged into coreboot/master: cpu/x86/mtrr: correct variable MTRR calculation around 1MiB boundary

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit a38677b6646fae7284d08fef706a77478c38c547
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Jul 21 14:26:34 2016 -0500

    cpu/x86/mtrr: correct variable MTRR calculation around 1MiB boundary
    
    The fixed MTRRs cover the range [0:1MiB). While calculating the
    variable MTRR usage the 1MiB boundary is checked such that
    an excessive number of MTRRs aren't used because of unnatural
    alignment at the low end of the physical address space. Howevever,
    those checks weren't inclusive of the 1MiB boundary. As such a
    variable MTRR could be used for a range which is actually covered
    by the fixed MTRRs when the end address is equal to 1MiB. Likewise,
    if the starting address of the range lands on the 1MiB boundary
    then more variable MTRRs are calculated in order to meet natural
    alignment requirements.
    
    Before:
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x0000000000100000 size 0x00060000 type 0
    0x0000000000100000 - 0x000000007b800000 size 0x7b700000 type 6
    0x000000007b800000 - 0x00000000b0000000 size 0x34800000 type 0
    0x00000000b0000000 - 0x00000000c0000000 size 0x10000000 type 1
    0x00000000c0000000 - 0x0000000100000000 size 0x40000000 type 0
    0x0000000100000000 - 0x0000000180000000 size 0x80000000 type 6
    CPU physical address size: 39 bits
    MTRR: default type WB/UC MTRR counts: 7/17.
    MTRR: WB selected as default type.
    MTRR: 0 base 0x0000000000000000 mask 0x0000007ffff00000 type 0
    MTRR: 1 base 0x000000007b800000 mask 0x0000007fff800000 type 0
    MTRR: 2 base 0x000000007c000000 mask 0x0000007ffc000000 type 0
    MTRR: 3 base 0x0000000080000000 mask 0x0000007fe0000000 type 0
    MTRR: 4 base 0x00000000a0000000 mask 0x0000007ff0000000 type 0
    MTRR: 5 base 0x00000000b0000000 mask 0x0000007ff0000000 type 1
    MTRR: 6 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0
    
    After:
    MTRR: Physical address space:
    0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
    0x00000000000a0000 - 0x0000000000100000 size 0x00060000 type 0
    0x0000000000100000 - 0x000000007b800000 size 0x7b700000 type 6
    0x000000007b800000 - 0x00000000b0000000 size 0x34800000 type 0
    0x00000000b0000000 - 0x00000000c0000000 size 0x10000000 type 1
    0x00000000c0000000 - 0x0000000100000000 size 0x40000000 type 0
    0x0000000100000000 - 0x0000000180000000 size 0x80000000 type 6
    CPU physical address size: 39 bits
    MTRR: default type WB/UC MTRR counts: 6/8.
    MTRR: WB selected as default type.
    MTRR: 0 base 0x000000007b800000 mask 0x0000007fff800000 type 0
    MTRR: 1 base 0x000000007c000000 mask 0x0000007ffc000000 type 0
    MTRR: 2 base 0x0000000080000000 mask 0x0000007fe0000000 type 0
    MTRR: 3 base 0x00000000a0000000 mask 0x0000007ff0000000 type 0
    MTRR: 4 base 0x00000000b0000000 mask 0x0000007ff0000000 type 1
    MTRR: 5 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0
    
    BUG=chrome-os-partner:55504
    
    Change-Id: I7feab38dfe135f5e596c9e67520378a406aa6866
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: https://review.coreboot.org/15780
    Reviewed-by: Furquan Shaikh <furquan at google.com>
    Reviewed-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See https://review.coreboot.org/15780 for details.

-gerrit