[coreboot-gerrit] New patch to review for coreboot: rockchip/rk3399: set CA drive strength to 48ohms

[Martin Roth (martinroth@google.com)]

Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15811

-gerrit

commit 9828f9c42abc8ae0c5fd0ff5fb0cec04acd306b9
Author: Lin Huang <hl at rock-chips.com>
Date:   Thu Jul 7 19:19:48 2016 +0800

    rockchip/rk3399: set CA drive strength to 48ohms
    
    As shown in testing, if CA use 34.3ohms drive strength, it leads
    to an overshoot. To fix this, change the drive strength to 48 ohms.
    
    BRANCH=none
    BUG=chrome-os-partner:54871
    TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass
    
    Change-Id: I8666474fc18391da14a3338611f962f2f08f36d0
    Signed-off-by: Martin Roth <martinroth at chromium.org>
    Original-Commit-Id: fbc1c13f9ab808fc907b2e3f9bde1d09f92980f1
    Original-Change-Id: I231f5b1bd45ff262686fbacbaf119a8a57fad27b
    Original-Signed-off-by: Lin Huang <hl at rock-chips.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/358761
    Original-Commit-Ready: Dan Shi <dshi at chromium.org>
    Original-Tested-by: Caesar Wang <wxt at rock-chips.com>
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
---
 src/soc/rockchip/rk3399/sdram.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c
index 293a0f2..c3db47b 100644
--- a/src/soc/rockchip/rk3399/sdram.c
+++ b/src/soc/rockchip/rk3399/sdram.c
@@ -182,32 +182,39 @@ static void set_ds_odt(u32 channel,
 
 	u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
 	u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p;
+	u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n;
 	u32 tsel_idle_select_n, tsel_wr_select_n, tsel_rd_select_n;
 	u32 reg_value;
 
 	if (sdram_params->dramtype == LPDDR4) {
 		tsel_rd_select_p = PHY_DRV_ODT_Hi_Z;
 		tsel_wr_select_p = PHY_DRV_ODT_40;
+		ca_tsel_wr_select_p = PHY_DRV_ODT_40;
 		tsel_idle_select_p = PHY_DRV_ODT_Hi_Z;
 
 		tsel_rd_select_n = PHY_DRV_ODT_240;
 		tsel_wr_select_n = PHY_DRV_ODT_40;
+		ca_tsel_wr_select_n = PHY_DRV_ODT_40;
 		tsel_idle_select_n = PHY_DRV_ODT_240;
 	} else if (sdram_params->dramtype == LPDDR3) {
 		tsel_rd_select_p = PHY_DRV_ODT_240;
 		tsel_wr_select_p = PHY_DRV_ODT_34_3;
+		ca_tsel_wr_select_p = PHY_DRV_ODT_48;
 		tsel_idle_select_p = PHY_DRV_ODT_240;
 
 		tsel_rd_select_n = PHY_DRV_ODT_Hi_Z;
 		tsel_wr_select_n = PHY_DRV_ODT_34_3;
+		ca_tsel_wr_select_n = PHY_DRV_ODT_48;
 		tsel_idle_select_n = PHY_DRV_ODT_Hi_Z;
 	} else {
 		tsel_rd_select_p = PHY_DRV_ODT_240;
 		tsel_wr_select_p = PHY_DRV_ODT_34_3;
+		ca_tsel_wr_select_p = PHY_DRV_ODT_34_3;
 		tsel_idle_select_p = PHY_DRV_ODT_240;
 
 		tsel_rd_select_n = PHY_DRV_ODT_240;
 		tsel_wr_select_n = PHY_DRV_ODT_34_3;
+		ca_tsel_wr_select_n = PHY_DRV_ODT_34_3;
 		tsel_idle_select_n = PHY_DRV_ODT_240;
 	}
 
@@ -243,7 +250,7 @@ static void set_ds_odt(u32 channel,
 	clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value);
 
 	/* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
-	reg_value = tsel_wr_select_n | (tsel_wr_select_p << 0x4);
+	reg_value = ca_tsel_wr_select_n | (ca_tsel_wr_select_p << 0x4);
 	clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
 	clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
 	clrsetbits_le32(&denali_phy[800], 0xff, reg_value);