[coreboot-gerrit] New patch to review for coreboot: intel/haswell: Remove useless MTRR clear

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15794

-gerrit

commit 8e4ab8d83ec4672b75484a97a56a0ca5e8fb5d45
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Fri Jul 22 00:01:33 2016 +0300

    intel/haswell: Remove useless MTRR clear
    
    At this state, variable MTRRs are disabled. We overwrite this MTRR entry
    before they are re-enabled.
    
    Change-Id: Ieedf90f65514d848905626e75be496e08f710d91
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/cpu/intel/haswell/cache_as_ram.inc | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc
index fe595fb..9cdb176 100644
--- a/src/cpu/intel/haswell/cache_as_ram.inc
+++ b/src/cpu/intel/haswell/cache_as_ram.inc
@@ -209,14 +209,6 @@ before_romstage:
 	andl    $~1, %eax
 	wrmsr
 
-	/* Clear MTRR that was used to cache MRC */
-	xorl	%eax, %eax
-	xorl	%edx, %edx
-	movl	$MTRR_PHYS_BASE(2), %ecx
-	wrmsr
-	movl	$MTRR_PHYS_MASK(2), %ecx
-	wrmsr
-
 	post_code(0x33)
 
 	/* Enable cache. */