[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Remove PEIM GFX from normal mode and S3 resume.

[Abhay Kumar (abhay.kumar@intel.com)]

Abhay Kumar (abhay.kumar at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14575

-gerrit

commit c08e65b8e3ff508aa5c0891e8f1995c49bcdca72
Author: Abhay Kumar <abhay.kumar at intel.com>
Date:   Thu Jul 14 18:43:54 2016 -0700

    soc/intel/apollolake: Remove PEIM GFX from normal mode and S3 resume.
    
    Do not pass VBT table to fsp in normal mode and S3 resume so that
    PEIM GFX will not get initialized.
    
    Change-Id: Iab7be3cceb0f80ae0273940b36fdd9c41bdb121e
    Signed-off-by: Abhay Kumar <abhay.kumar at intel.com>
---
 src/soc/intel/apollolake/chip.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 60cdb50..26d2fce 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -34,6 +34,7 @@
 #include <spi-generic.h>
 #include <soc/pm.h>
 #include <soc/p2sb.h>
+#include <bootmode.h>
 
 #include "chip.h"
 
@@ -194,7 +195,7 @@ static void soc_init(void *data)
 	struct global_nvs_t *gnvs;
 
 	/* Save VBT info and mapping */
-	if (locate_vbt(&vbt_rdev) != CB_ERR)
+	if ((!acpi_is_wakeup_s3()) && display_init_required() && (locate_vbt(&vbt_rdev) != CB_ERR))
 		vbt = rdev_mmap_full(&vbt_rdev);
 
 	/* Snapshot the current GPIO IRQ polarities. FSP is setting a