[coreboot-gerrit] Patch set updated for coreboot: mainboard/intel/kblrvp: Enable building without EC
Naveen Krishna (naveenkrishna.ch@gmail.com)
gerrit at coreboot.org
Thu Jul 21 18:23:43 CEST 2016
Naveen Krishna (naveenkrishna.ch at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15770
-gerrit
commit feee412b3f00c7c7bec5fd8d722d51a46062c601
Author: Naveen Krishna Chatradhi <naveenkrishna.ch at intel.com>
Date: Fri Jun 10 19:21:55 2016 +0530
mainboard/intel/kblrvp: Enable building without EC
Kabylake RVP does not have EC. Compile chromeec functions
based on the definition of CONFIG_EC_GOOGLE_CHROMEEC,
return 0 otherwise.
Also, define weak functions to avoid compilation issues if the EC
symbols are not selected.
BUG=chrome-os-partner:55399
TEST=Build for kabylake RVP board.
#make menuconfig, select Kabylake SoC, kblrvp3 board.
#make compiles
Change-Id: Iba15083e815a71e657cb2cec6a2eadd4a300bf6c
Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch at intel.com>
---
src/mainboard/intel/kblrvp/Kconfig | 5 ----
src/mainboard/intel/kblrvp/acpi/superio.asl | 6 ++++-
src/mainboard/intel/kblrvp/boardid.c | 6 +++--
src/mainboard/intel/kblrvp/car.c | 5 +++-
src/mainboard/intel/kblrvp/chromeos.c | 37 +++++++++++++++++++++++------
src/mainboard/intel/kblrvp/mainboard.c | 6 +++--
src/mainboard/intel/kblrvp/smihandler.c | 3 ++-
7 files changed, 49 insertions(+), 19 deletions(-)
diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig
index 85323f9..70e62eb 100644
--- a/src/mainboard/intel/kblrvp/Kconfig
+++ b/src/mainboard/intel/kblrvp/Kconfig
@@ -4,11 +4,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select BOARD_ID_AUTO
select BOARD_ROMSIZE_KB_16384
- select EC_GOOGLE_CHROMEEC
- select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
- select EC_GOOGLE_CHROMEEC_LPC
- select EC_GOOGLE_CHROMEEC_MEC
- select EC_GOOGLE_CHROMEEC_PD
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
diff --git a/src/mainboard/intel/kblrvp/acpi/superio.asl b/src/mainboard/intel/kblrvp/acpi/superio.asl
index 803d2e3..5a949ff 100644
--- a/src/mainboard/intel/kblrvp/acpi/superio.asl
+++ b/src/mainboard/intel/kblrvp/acpi/superio.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015-2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -14,11 +14,15 @@
*/
/* mainboard configuration */
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
#include "../ec.h"
+#endif
#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
/* ACPI code for EC SuperIO functions */
#include <ec/google/chromeec/acpi/superio.asl>
+#endif
diff --git a/src/mainboard/intel/kblrvp/boardid.c b/src/mainboard/intel/kblrvp/boardid.c
index c374453..978f8cb0 100644
--- a/src/mainboard/intel/kblrvp/boardid.c
+++ b/src/mainboard/intel/kblrvp/boardid.c
@@ -21,8 +21,10 @@ uint8_t board_id(void)
{
MAYBE_STATIC int id = -1;
- if (id < 0)
- id = google_chromeec_get_board_version();
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) {
+ if (id < 0)
+ id = google_chromeec_get_board_version();
+ }
return id;
}
diff --git a/src/mainboard/intel/kblrvp/car.c b/src/mainboard/intel/kblrvp/car.c
index 7791b92..d9d43d7 100644
--- a/src/mainboard/intel/kblrvp/car.c
+++ b/src/mainboard/intel/kblrvp/car.c
@@ -13,7 +13,9 @@
* GNU General Public License for more details.
*/
+#ifdef CONFIG_EC_GOOGLE_CHROMEEC
#include <ec/google/chromeec/ec.h>
+#endif
#include <fsp/car.h>
#include <soc/gpio.h>
#include "gpio.h"
@@ -29,7 +31,8 @@ static void early_config_gpio(void)
void car_mainboard_post_console_init(void)
{
/* Ensure the EC and PD are in the right mode for recovery */
- google_chromeec_early_init();
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ google_chromeec_early_init();
early_config_gpio();
}
diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c
index 108cb3b..90d7fb6 100644
--- a/src/mainboard/intel/kblrvp/chromeos.c
+++ b/src/mainboard/intel/kblrvp/chromeos.c
@@ -50,7 +50,10 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_lid_switch(void)
{
/* Read lid switch state from the EC. */
- return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN);
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN);
+ else
+ return 0;
}
int get_developer_mode_switch(void)
@@ -62,19 +65,27 @@ int get_developer_mode_switch(void)
int get_recovery_mode_switch(void)
{
/* Check for dedicated recovery switch first. */
- if (google_chromeec_get_switches() & EC_SWITCH_DEDICATED_RECOVERY)
- return 1;
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) {
+ if (google_chromeec_get_switches() & EC_SWITCH_DEDICATED_RECOVERY)
+ return 1;
/* Otherwise check if the EC has posted the keyboard recovery event. */
- return !!(google_chromeec_get_events_b() &
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+ return !!(google_chromeec_get_events_b() &
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+ } else {
+ return 0;
+ }
}
int clear_recovery_mode_switch(void)
{
/* Clear keyboard recovery event. */
- return google_chromeec_clear_events_b(
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) {
+ return google_chromeec_clear_events_b(
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+ } else {
+ return 0;
+ }
}
int get_write_protect_state(void)
@@ -82,3 +93,15 @@ int get_write_protect_state(void)
/* Read PCH_WP GPIO. */
return gpio_get(GPIO_PCH_WP);
}
+
+#if (!IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+__attribute__((weak)) int vboot_save_hash(void *digest, size_t digest_size)
+{
+ return 0;
+}
+
+__attribute__((weak)) int vboot_retrieve_hash(void *digest, size_t digest_size)
+{
+ return 0;
+}
+#endif
diff --git a/src/mainboard/intel/kblrvp/mainboard.c b/src/mainboard/intel/kblrvp/mainboard.c
index 7cc64dd..0da54f3 100644
--- a/src/mainboard/intel/kblrvp/mainboard.c
+++ b/src/mainboard/intel/kblrvp/mainboard.c
@@ -26,11 +26,12 @@
#include "gpio.h"
static const char *oem_id_maxim = "INTEL";
-static const char *oem_table_id_maxim = "SCRDMAX";
+static const char *oem_table_id_maxim = "KBLRVPMAX";
static void mainboard_init(device_t dev)
{
- mainboard_ec_init();
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ mainboard_ec_init();
}
static uint8_t select_audio_codec(void)
@@ -102,5 +103,6 @@ static void mainboard_enable(device_t dev)
}
struct chip_operations mainboard_ops = {
+ CHIP_NAME("Intel KBLRVP Mainboard")
.enable_dev = mainboard_enable,
};
diff --git a/src/mainboard/intel/kblrvp/smihandler.c b/src/mainboard/intel/kblrvp/smihandler.c
index 0fdb571..17e0a92 100644
--- a/src/mainboard/intel/kblrvp/smihandler.c
+++ b/src/mainboard/intel/kblrvp/smihandler.c
@@ -49,7 +49,8 @@ int mainboard_io_trap_handler(int smif)
void mainboard_smi_gpi_handler(const struct gpi_status *sts)
{
- if (gpi_status_get(sts, EC_SMI_GPI))
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) &&
+ gpi_status_get(sts, EC_SMI_GPI))
chromeec_smi_process_events();
}
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