[coreboot-gerrit] Patch set updated for coreboot: mainboard/google/reef: indicate dual rank LPDDR4 skus
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Thu Jul 21 17:07:54 CEST 2016
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15772
-gerrit
commit 8c411005eed5cc383c7d5e7eba5a421ecbd382b5
Author: Aaron Durbin <adurbin at chromium.org>
Date: Thu Jul 21 10:00:39 2016 -0500
mainboard/google/reef: indicate dual rank LPDDR4 skus
The 16Gb devices use two ranks per channel within the DRAM module.
Indicate that to the memory init code so that the correct rank
enable settings are used.
BUG=chrome-os-partner:55446
Change-Id: Ib5dba6f9ed248750d68b726996c71def9b75961e
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/mainboard/google/reef/romstage.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c
index 8b7c7a3..a993317 100644
--- a/src/mainboard/google/reef/romstage.c
+++ b/src/mainboard/google/reef/romstage.c
@@ -76,6 +76,8 @@ static const struct lpddr4_sku skus[] = {
.speed = LP4_SPEED_2400,
.ch0_density = LP4_16Gb_DENSITY,
.ch1_density = LP4_16Gb_DENSITY,
+ .ch0_dual_rank = 1,
+ .ch1_dual_rank = 1,
},
/* K4F8E304HB-MGCJ - both logical channels */
[1] = {
@@ -88,6 +90,8 @@ static const struct lpddr4_sku skus[] = {
.speed = LP4_SPEED_2400,
.ch0_density = LP4_16Gb_DENSITY,
.ch1_density = LP4_16Gb_DENSITY,
+ .ch0_dual_rank = 1,
+ .ch1_dual_rank = 1,
/* MT53B256M32D1NP-062 WT:C - both logical channels */
},
[3] = {
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