[coreboot-gerrit] Patch set updated for coreboot: mainboard/google/reef: reverse the memory config bits

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15753

-gerrit

commit 36d1670a96af582dfc5ede6f9181e94755e659f2
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Jul 19 17:39:05 2016 -0500

    mainboard/google/reef: reverse the memory config bits
    
    I mistakenly assumed the order of the bits matched how one
    would assign values as they wrote them msb .. lsb. However, the
    gpio lib doesn't do that. Correct the order so that values are
    read out correctly.
    
    BUG=chrome-os-partner:54949t
    
    Change-Id: I5304dfe2ba6f8eb073acab3377327167573ec2cc
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/reef/romstage.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c
index 2c68b60..8b7c7a3 100644
--- a/src/mainboard/google/reef/romstage.c
+++ b/src/mainboard/google/reef/romstage.c
@@ -112,7 +112,10 @@ static const struct lpddr4_cfg lp4cfg = {
 void mainboard_memory_init_params(struct FSPM_UPD *memupd)
 {
 	int mem_sku;
-	gpio_t pads[] = { MEM_CONFIG3, MEM_CONFIG2, MEM_CONFIG1, MEM_CONFIG0 };
+	gpio_t pads[] = {
+		[3] = MEM_CONFIG3, [2] = MEM_CONFIG2,
+		[1] = MEM_CONFIG1, [0] = MEM_CONFIG0,
+	};
 
 	/*
 	 * Read memory SKU id with internal pullups enabled to handle