[coreboot-gerrit] Patch merged into coreboot/master: drivers/intel/fsp2_0: honor FSP revision for memory training data
gerrit at coreboot.org
gerrit at coreboot.org
Tue Jul 19 20:18:40 CEST 2016
the following patch was just integrated into master:
commit f0ec82450b86112d8e95b38d91d58f9afdbbb846
Author: Aaron Durbin <adurbin at chromium.org>
Date: Mon Jul 18 11:24:36 2016 -0500
drivers/intel/fsp2_0: honor FSP revision for memory training data
Utilizing the FSP revision while saving the memory training data is
important because it means when the FSP is updated the memory training
is redone. The previous implementation was just using '0' as a revision.
Because of that behavior a retrain would not have been done on an FSP
upgrade.
BUG=chrome-os-partner:52679
Change-Id: I1430bd78c770a840d2deff2476f47150c02cf27d
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-on: https://review.coreboot.org/15744
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan at google.com>
Reviewed-by: Andrey Petrov <andrey.petrov at intel.com>
Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
See https://review.coreboot.org/15744 for details.
-gerrit
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