hakim giydan (hgiydan at marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15335
-gerrit
commit a10eb24c7a9b5e79805c87004db0ff165d1a2b03
Author: Hakim Giydan <hgiydan at marvell.com>
Date: Tue Jul 19 09:13:33 2016 -0700
arch: Add ARMv7-R configuration
This change adds armv7-r configuration for romstage and verstage,
and any other files needed to initialize an armv7-r processor.
ARMv7-R is an ARM processor based on the Cortex-R series.
Currently, there is already support for Cortex-M and Coretex-A
series. The same files had been renamed and reused for Cortex-R
series as well.
Change-Id: If94415d07fd6bd96c43d087374f609a2211f1885
Signed-off-by: Hakim Giydan <hgiydan at marvell.com>
---
src/arch/arm/armv7/Kconfig | 8 ++
src/arch/arm/armv7/Makefile.inc | 27 ++++++-
src/arch/arm/armv7/cpu_r.S | 151 ++++++++++++++++++++++++++++++++++++++
src/arch/arm/armv7/exception_m.c | 36 ---------
src/arch/arm/armv7/exception_mr.c | 36 +++++++++
util/xcompile/xcompile | 2 +-
6 files changed, 222 insertions(+), 38 deletions(-)
diff --git a/src/arch/arm/armv7/Kconfig b/src/arch/arm/armv7/Kconfig
index 0ab3542..4fe3fd7 100644
--- a/src/arch/arm/armv7/Kconfig
+++ b/src/arch/arm/armv7/Kconfig
@@ -19,3 +19,11 @@ config ARCH_BOOTBLOCK_ARMV7_M
config ARCH_VERSTAGE_ARMV7_M
def_bool n
select ARCH_VERSTAGE_ARM
+
+config ARCH_VERSTAGE_ARMV7_R
+ def_bool n
+ select ARCH_VERSTAGE_ARM
+
+config ARCH_ROMSTAGE_ARMV7_R
+ def_bool n
+ select ARCH_ROMSTAGE_ARM
diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc
index 2e9c49c..d839b9d 100644
--- a/src/arch/arm/armv7/Makefile.inc
+++ b/src/arch/arm/armv7/Makefile.inc
@@ -18,8 +18,10 @@
armv7_flags = -mthumb -I$(src)/arch/arm/include/armv7/ -D__COREBOOT_ARM_ARCH__=7
armv7-a_flags = -march=armv7-a $(armv7_flags)
armv7-m_flags = -march=armv7-m $(armv7_flags)
+armv7-r_flags = -march=armv7-r $(armv7_flags)
armv7_asm_flags = -Wa,-mthumb -Wa,-mimplicit-it=always -Wa,-mno-warn-deprecated
+armv7-r_asm_flags = $(armv7-r_flags) $(armv7_asm_flags)
###############################################################################
# bootblock
@@ -46,7 +48,7 @@ bootblock-S-ccopts += $(armv7_asm_flags)
ifneq ($(CONFIG_BOOTBLOCK_CUSTOM),y)
bootblock-y += bootblock_m.S
endif
-bootblock-y += exception_m.c
+bootblock-y += exception_mr.c
bootblock-y += cache_m.c
endif # CONFIG_ARCH_BOOTBLOCK_ARMV7
@@ -73,6 +75,17 @@ libverstage-S-ccopts += $(armv7_asm_flags)
verstage-generic-ccopts += $(armv7-m_flags)
verstage-S-ccopts += $(armv7_asm_flags)
+else ifeq ($(CONFIG_ARCH_VERSTAGE_ARMV7_R),y)
+libverstage-generic-ccopts += $(armv7-r_flags)
+libverstage-S-ccopts += $(armv7-r_asm_flags)
+verstage-generic-ccopts += $(armv7-r_flags)
+verstage-S-ccopts += $(armv7-r_asm_flags)
+
+verstage-y += cache.c
+verstage-y += cpu_r.S
+verstage-y += exception_mr.c
+verstage-y += mmu.c
+
endif # CONFIG_ARCH_VERSTAGE_ARMV7_M
################################################################################
@@ -91,6 +104,18 @@ romstage-S-ccopts += $(armv7_asm_flags)
rmodules_arm-generic-ccopts += $(armv7-a_flags)
rmodules_arm-S-ccopts += $(armv7_asm_flags)
+else ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV7_R),y)
+romstage-y += cache.c
+romstage-y += cpu_r.S
+romstage-y += exception_mr.c
+romstage-y += mmu.c
+
+romstage-generic-ccopts += $(armv7-r_flags)
+romstage-S-ccopts += $(armv7-r_asm_flags)
+
+rmodules_arm-generic-ccopts += $(armv7-r_flags)
+rmodules_arm-S-ccopts += $(armv7-r_asm_flags)
+
endif # CONFIG_ARCH_ROMSTAGE_ARMV7
###############################################################################
diff --git a/src/arch/arm/armv7/cpu_r.S b/src/arch/arm/armv7/cpu_r.S
new file mode 100644
index 0000000..48f9b82
--- /dev/null
+++ b/src/arch/arm/armv7/cpu_r.S
@@ -0,0 +1,151 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2010 Per Odlund <per.odlund at armagedon.se>
+ * Copyright (c) 2014 Google Inc.
+ * Copyright (c) 2016 Marvell Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <arch/asm.h>
+
+/*
+ * Dcache invalidations by set/way work by passing a [way:sbz:set:sbz:level:0]
+ * bitfield in a register to the appropriate MCR instruction. This algorithm
+ * works by initializing a bitfield with the highest-numbered set and way, and
+ * generating a "set decrement" and a "way decrement". The former just contains
+ * the LSB of the set field, but the latter contains the LSB of the way field
+ * minus the highest valid set field... such that when you subtract it from a
+ * [way:0:level] field you end up with a [way - 1:highest_set:level] field
+ * through the magic of double subtraction. It's quite ingenius, really.
+ * Takes care to only use r0-r3 and ip so it's pefectly ABI-compatible without
+ * needing to write to memory.
+ *
+ * THIS FUNCTION MUST PRESERVE THE VALUE OF r10
+ */
+
+.macro dcache_apply_all crm
+ dsb
+ mov r3, #-2 @ initialize level so that we start at 0
+
+1: @next_level
+ add r3, r3, #2 @ increment level
+
+ mrc p15, 1, r0, c0, c0, 1 @ read CLIDR
+ and ip, r0, #0x07000000 @ narrow to LoC
+ lsr ip, ip, #23 @ left align LoC (low 4 bits)
+ cmp r3, ip @ compare
+ bge 3f @done @ else fall through (r0 == CLIDR)
+
+ add r2, r3, r3, lsr #1 @ r2 = (level << 1) * 3 / 2
+ mov r1, r0, lsr r2 @ r1 = cache type
+ and r1, r1, #7
+ cmp r1, #2 @ is it data or i&d?
+ blt 1b @next_level @ nope, skip level
+
+ mcr p15, 2, r3, c0, c0, 0 @ select cache level
+ isb
+ mrc p15, 1, r0, c0, c0, 0 @ read CCSIDR
+
+ ubfx ip, r0, #0, #3 @ get linesize from CCSIDR
+ add ip, ip, #4 @ apply bias
+ ubfx r2, r0, #13, #15 @ get numsets - 1 from CCSIDR
+ lsl r2, r2, ip @ shift to set position
+ orr r3, r3, r2 @ merge set into way/set/level
+ mov r1, #1
+ lsl r1, r1, ip @ r1 = set decr
+
+ ubfx ip, r0, #3, #10 @ get numways - 1 from [to be discarded] CCSIDR
+ clz r2, ip @ number of bits to MSB of way
+ lsl ip, ip, r2 @ shift by that into way position
+ mov r0, #1
+ lsl r2, r0, r2 @ r2 now contains the way decr
+ mov r0, r3 @ get sets/level (no way yet)
+ orr r3, r3, ip @ merge way into way/set/level
+ bfc r0, #0, #4 @ clear low 4 bits (level) to get numset - 1
+ sub r2, r2, r0 @ subtract from way decr
+
+ /* r3 = ways/sets/level, r2 = way decr, r1 = set decr, r0 and ip are free */
+2: mcr p15, 0, r3, c7, \crm, 2 @ writeback and/or invalidate line
+ cmp r3, #15 @ are we done with this level (way/set == 0)
+ bls 1b @next_level @ yes, go to next level
+ lsr r0, r3, #4 @ clear level bits leaving only way/set bits
+ lsls r0, r0, #14 @ clear way bits leaving only set bits
+ subne r3, r3, r1 @ non-zero?, decrement set #
+ subeq r3, r3, r2 @ zero?, decrement way # and restore set count
+ b 2b
+
+3: @done
+ mov r0, #0 @ default back to cache level 0
+ mcr p15, 2, r0, c0, c0, 0 @ select cache level
+ dsb
+ isb
+ bx lr
+.endm
+
+/*
+ * Bring an ARM processor we just gained control of (e.g. from IROM) into a
+ * known state regarding caches/SCTLR. Completely cleans and invalidates
+ * icache/dcache, and dcache (if active), and enables unaligned
+ * accesses, icache and branch prediction (if inactive). Clobbers r4 and r5.
+ *
+ * THIS FUNCTION MUST PRESERVE THE VALUE OF r10
+ */
+ENTRY(arm_init_caches)
+ /* r4: SCTLR, return address: r5 (stay valid for the whole function) */
+ mov r5, lr
+ mrc p15, 0, r4, c1, c0, 0
+
+ /* Activate ICache (12) and Branch Prediction (11) already for speed */
+ orr r4, # (1 << 11) | (1 << 12)
+ mcr p15, 0, r4, c1, c0, 0
+
+ /* Flush and invalidate dcache in ascending order */
+ bl dcache_invalidate_all
+
+ /* Deactivate Alignment Check (1) and DCache (2) */
+ and r4, # ~(1 << 1) & ~(1 << 2)
+ mcr p15, 0, r4, c1, c0, 0
+
+ /* Invalidate icache for good measure */
+ mcr p15, 0, r0, c7, c5, 0
+
+ dsb
+ isb
+
+ bx r5
+ENDPROC(arm_init_caches)
+
+ENTRY(dcache_invalidate_all)
+ dcache_apply_all crm=c6
+ENDPROC(dcache_invalidate_all)
+
+ENTRY(dcache_clean_all)
+ dcache_apply_all crm=c10
+ENDPROC(dcache_clean_all)
+
+ENTRY(dcache_clean_invalidate_all)
+ dcache_apply_all crm=c14
+ENDPROC(dcache_clean_invalidate_all)
diff --git a/src/arch/arm/armv7/exception_m.c b/src/arch/arm/armv7/exception_m.c
deleted file mode 100644
index d76cc6a..0000000
--- a/src/arch/arm/armv7/exception_m.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is part of the libpayload project.
- *
- * Copyright 2013 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <arch/exception.h>
-#include <console/console.h>
-
-void exception_init(void)
-{
- printk(BIOS_DEBUG, "Exception handlers not installed.\n");
-}
diff --git a/src/arch/arm/armv7/exception_mr.c b/src/arch/arm/armv7/exception_mr.c
new file mode 100644
index 0000000..d76cc6a
--- /dev/null
+++ b/src/arch/arm/armv7/exception_mr.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <arch/exception.h>
+#include <console/console.h>
+
+void exception_init(void)
+{
+ printk(BIOS_DEBUG, "Exception handlers not installed.\n");
+}
diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index 13a0e8f..1a9c38c 100755
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -316,7 +316,7 @@ arch_config_arm() {
TBFDARCHS="littlearm"
TCLIST="armv7-a armv7a arm"
TWIDTH="32"
- TSUPP="arm armv4 armv7 armv7_m"
+ TSUPP="arm armv4 armv7 armv7_m armv7_r"
TABI="eabi"
}