[coreboot-gerrit] Patch set updated for coreboot: arch/riscv: Enable unaligned load handling

[Jonathan Neuschäfer (j.neuschaefer@gmx.net)]

Jonathan Neuschäfer (j.neuschaefer at gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15590

-gerrit

commit 51f9e60805a4fa7fc3596b8886c585cc11c4194e
Author: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Date:   Thu Jul 7 20:53:29 2016 +0200

    arch/riscv: Enable unaligned load handling
    
    Change-Id: If1c63971335a6e2963e01352acfa4bd0c1d86bc2
    Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
---
 src/arch/riscv/include/arch/exception.h | 2 +-
 src/arch/riscv/trap_handler.c           | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/arch/riscv/include/arch/exception.h b/src/arch/riscv/include/arch/exception.h
index 28b9279..fc57b3b 100644
--- a/src/arch/riscv/include/arch/exception.h
+++ b/src/arch/riscv/include/arch/exception.h
@@ -55,7 +55,7 @@ static inline void exception_init(void)
 
 void trap_handler(trapframe* tf);
 void handle_supervisor_call(trapframe* tf);
-void handleMisalignedLoad(trapframe *tf);
+void handle_misaligned_load(trapframe *tf);
 void handle_misaligned_store(trapframe *tf);
 
 #endif
diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index 5b4d0b1..193be61 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -118,7 +118,7 @@ void trap_handler(trapframe *tf) {
 			break;
 		case 4:
 			printk(BIOS_DEBUG, "Trap: Load address misaligned\n");
-			//handleMisalignedLoad(tf);
+			handle_misaligned_load(tf);
 			break;
 		case 5:
 			printk(BIOS_DEBUG, "Trap: Load access fault\n");
@@ -161,7 +161,7 @@ void trap_handler(trapframe *tf) {
 	while(1);
 }
 
-void handleMisalignedLoad(trapframe *tf) {
+void handle_misaligned_load(trapframe *tf) {
 	printk(BIOS_DEBUG, "Trapframe ptr: %p\n", tf);
 	printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]);
 	insn_t faultingInstruction = 0;