[coreboot-gerrit] Patch set updated for coreboot: amd/agesa/f16kb: Allow SATA Gen3

[Fabian Kunkel (fabi@adv.bruhnspace.com)]

Fabian Kunkel (fabi at adv.bruhnspace.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15728

-gerrit

commit 3611fa62498a39579192b339b590560b7605e8f1
Author: Fabian Kunkel <fabi at adv.bruhnspace.com>
Date:   Mon Jul 18 17:39:28 2016 +0200

    amd/agesa/f16kb: Allow SATA Gen3
    
    The SATA speed is limited to Gen1/2.
    SataSetMaxGen2 is a power saving option,
    which is on in the default structure and also hard coded.
    This patch disables the power saving option and
    enables Gen3 support.
    Patch is tested with bap/e20xx board, Lubuntu 16.04 Kernel 4.4.
    $ dmesg | grep ahci #before patch
    ahci 0000:00:11.0: AHCI 0001.0300 32 slots 2 ports 3 Gbps 0x3 impl SATA mode
    $ dmesg | grep ahci #after patch
    ahci 0000:00:11.0: AHCI 0001.0300 32 slots 2 ports 6 Gbps 0x3 impl SATA mode
    
    Change-Id: I17a493b876a4be3236736b2116b331e465b159af
    Signed-off-by: Fabian Kunkel <fabi at adv.bruhnspace.com>
---
 .../amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c   | 2 +-
 .../agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataResetService.c  | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c
index f638e71..11cf6e1 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c
@@ -162,7 +162,7 @@ FCH_DATA_BLOCK   InitEnvCfgDefault = {
       0,                     // SataModeReg
       TRUE,                  // SataEnable
       0,                     // Sata6AhciCap
-      TRUE,                  // SataSetMaxGen2
+      FALSE,                 // SataSetMaxGen2
       FALSE,                 // IdeEnable
       01,                    // SataClkMode
     },
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataResetService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataResetService.c
index 9b14467..3142899 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataResetService.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataResetService.c
@@ -78,7 +78,6 @@ FchInitResetSataProgram (
   if ( LocalCfgPtr->SataSetMaxGen2 ) {
     FchSataMode |= 0x04;
   }
-  FchSataMode |= 0x04;
 
   RwPci (((SATA_BUS_DEV_FUN << 16) + 0x0A0), AccessWidth8, (UINT32)~(BIT2 + BIT3 + BIT4 + BIT5 + BIT6), 0, StdHeader);
   FchSataClkMode = LocalCfgPtr->SataClkMode;