[coreboot-gerrit] Patch set updated for coreboot: drivers/intel/fsp2_0: set BootLoaderTolumSize generically

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15738

-gerrit

commit 793939b5913bfa1715feccf1ec2ca10ed835ab3c
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Jul 15 22:32:28 2016 -0500

    drivers/intel/fsp2_0: set BootLoaderTolumSize generically
    
    The amount of reserved memory just below the DRAM limit in
    32-bit space is defined in the FSP 2.0 specification within
    the FSPM_ARCH_UPD structure. There's no need to make the
    chipset code set the same value as needed for coreboot.
    The chipset code can always change the value if it needs
    after the common setting being applied.
    
    Remove the call in soc/intel/apollolake as it's no longer
    needed.
    
    BUG=chrome-os-partner:52679
    
    Change-Id: I69a1fee7a7b53c109afd8ee0f03cb8506584d571
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/drivers/intel/fsp2_0/memory_init.c | 4 ++++
 src/soc/intel/apollolake/romstage.c    | 2 --
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index 45516aa..5363fdd 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -13,6 +13,7 @@
 
 #include <arch/io.h>
 #include <arch/cpu.h>
+#include <cbmem.h>
 #include <console/console.h>
 #include <fsp/api.h>
 #include <fsp/util.h>
@@ -42,6 +43,9 @@ static enum fsp_status do_fsp_memory_init(void **hob_list_ptr,
 	/* Copy the default values from the UPD area */
 	memcpy(&fspm_upd, upd, sizeof(fspm_upd));
 
+	/* Reserve enough memory under TOLUD to save CBMEM header */
+	fspm_upd.FspmArchUpd.BootLoaderTolumSize = cbmem_overhead_size();
+
 	/* Give SoC and mainboard a chance to update the UPD */
 	platform_fsp_memory_init_params_cb(&fspm_upd);
 
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 1a860e8..ddbfaa4 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -213,8 +213,6 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd)
 
 	/* Do NOT let FSP do any GPIO pad configuration */
 	mupd->FspmConfig.PreMemGpioTablePtr = (uintptr_t) NULL;
-	/* Reserve enough memory under TOLUD to save CBMEM header */
-	mupd->FspmArchUpd.BootLoaderTolumSize = cbmem_overhead_size();
 	/*
 	 * FSPM_UPD passed here is populated with default values provided by
 	 * the blob itself. We let FSPM use top of CAR region of the size it