[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Implement reset_prepare()
Andrey Petrov (andrey.petrov@intel.com)
gerrit at coreboot.org
Mon Jul 18 21:14:53 CEST 2016
Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15721
-gerrit
commit c092ba420b98f382abf4a35c9caf01cc8cb5f754
Author: Andrey Petrov <andrey.petrov at intel.com>
Date: Fri Jul 15 14:44:48 2016 -0700
soc/intel/apollolake: Implement reset_prepare()
At first boot CSE spends long time preparing media for use. As result
it may not be able to deal with a CPU reset. Add reset_prepare()
callback that polls CSE readiness.
BUG=chrome-os-partner:55055
TEST=build with release version of fsp, reboot, observe polling for
CSE, then proper reboot happening
Change-Id: I639ef900b97132f1a7f269bb864d70009df9fdfe
Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
src/soc/intel/apollolake/reset.c | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/src/soc/intel/apollolake/reset.c b/src/soc/intel/apollolake/reset.c
index 644d88d..f759bac 100644
--- a/src/soc/intel/apollolake/reset.c
+++ b/src/soc/intel/apollolake/reset.c
@@ -13,11 +13,47 @@
* GNU General Public License for more details.
*/
+#include <console/console.h>
+#include <delay.h>
#include <reset.h>
+#include <soc/heci.h>
#include <soc/pm.h>
+#include <timer.h>
+
+#define CSE_WAIT_MAX_MS 1000
void global_reset(void)
{
global_reset_enable(1);
hard_reset();
}
+
+void reset_prepare(void)
+{
+ struct stopwatch sw;
+
+ /*
+ * If CSE state is something else than 'normal', it is probably in some
+ * recovery state. In this case there is no point in waiting for it to
+ * get ready so we cross fingers and reset.
+ */
+ if (!heci_cse_normal()) {
+ printk(BIOS_DEBUG, "CSE is not in normal state, resetting\n");
+ return;
+ }
+
+ /* Reset if CSE is ready */
+ if (heci_cse_done())
+ return;
+
+ printk(BIOS_SPEW, "CSE is not yet ready, waiting\n");
+ stopwatch_init_msecs_expire(&sw, CSE_WAIT_MAX_MS);
+ while (!heci_cse_done()) {
+ if (stopwatch_expired(&sw)) {
+ printk(BIOS_SPEW, "CSE timed out. Resetting\n");
+ return;
+ }
+ mdelay(1);
+ }
+ printk(BIOS_SPEW, "CSE took %lu ms\n", stopwatch_duration_msecs(&sw));
+}
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