[coreboot-gerrit] New patch to review for coreboot: soc/intel/common: Add reset_prepare() for common reset

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15720

-gerrit

commit c6ab8b41c105e8898ee8a643244ff3cd76e5c39d
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Fri Jul 15 13:31:09 2016 -0700

    soc/intel/common: Add reset_prepare() for common reset
    
    Some Intel SoC may need preparation before reset can be properly
    handled. Add callback that chip/soc code can implement.
    
    BUG=chrome-os-partner:55055
    
    Change-Id: I45857838e1a306dbcb9ed262b55e7db88a8944e5
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/include/reset.h          | 3 ++-
 src/soc/intel/common/reset.c | 5 +++++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/include/reset.h b/src/include/reset.h
index 95ba608..67f58db 100644
--- a/src/include/reset.h
+++ b/src/include/reset.h
@@ -10,5 +10,6 @@ void soft_reset(void);
 void cpu_reset(void);
 /* Some Intel SoCs use a special reset that is specific to SoC */
 void global_reset(void);
-
+/* Some Intel SoCs may need to prepare/wait before reset */
+void reset_prepare(void);
 #endif
diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c
index 79547c6..263d235 100644
--- a/src/soc/intel/common/reset.c
+++ b/src/soc/intel/common/reset.c
@@ -27,6 +27,7 @@
 
 void hard_reset(void)
 {
+	reset_prepare();
 	/* S0->S5->S0 trip. */
 	outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT);
 	while (1)
@@ -35,6 +36,7 @@ void hard_reset(void)
 
 void soft_reset(void)
 {
+	reset_prepare();
 	/* PMC_PLTRST# asserted. */
 	outb(RST_CPU | SYS_RST, RST_CNT);
 	while (1)
@@ -43,8 +45,11 @@ void soft_reset(void)
 
 void cpu_reset(void)
 {
+	reset_prepare();
 	/* Sends INIT# to CPU */
 	outb(RST_CPU, RST_CNT);
 	while (1)
 		hlt();
 }
+
+void __attribute__ ((weak)) reset_prepare(void) { /* do nothing */ }