[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/apollolake: Properly disable PCIe root ports

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit d779605c29a1630a256c8a1c4966214c580481ec
Author: Kane Chen <kane.chen at intel.com>
Date:   Mon Jul 11 12:17:13 2016 +0800

    soc/intel/apollolake: Properly disable PCIe root ports
    
    1. The hotplug feature needs to be disabled
       so that pcie root ports will be disabled by fsp
    2. Correct PcieRootPortEn mapping.
    The correct mapping should be like below
    PcieRootPortEn[0] ==>  00:14.0
    PcieRootPortEn[1] ==>  00:14.1
    PcieRootPortEn[2] ==>  00:13.0
    PcieRootPortEn[3] ==>  00:13.1
    PcieRootPortEn[4] ==>  00:13.2
    PcieRootPortEn[5] ==>  00:13.3
    
    BUG=chrome-os-partner:54288
    BRANCH=None
    TEST=Checked pcie root port is disabled properly
    and make sure pcie ports are coalesced.
    Also make sure the device will still be enabled after coalescence
    when pcie on function 0 is disabled devicetree
    
    Change-Id: I39c482a0c068ddc2cc573499480c3fe6a52dd5eb
    Signed-off-by: Kane Chen <kane.chen at intel.com>
    Reviewed-on: https://review.coreboot.org/15595
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/15595 for details.

-gerrit