[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Use custom reset calls

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15714

-gerrit

commit 6218069c1b03158f5a72c8d16cb0bb2fd1f43fdc
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Thu Jun 9 21:35:50 2016 -0700

    soc/intel/apollolake: Use custom reset calls
    
    Apollolake may not be able to handle reset if CSE is busy, which
    is likely to happen on first boot. Add custom reset calls that
    spin until CSE is 'ready'.
    
    BUG=chrome-os-partner:55055
    TEST=testing needed, issue not reproduced yet
    
    Change-Id: If0ec56db3864d500acc93d2b363a78a6cd7632db
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/soc/intel/apollolake/Kconfig |  2 +-
 src/soc/intel/apollolake/reset.c | 59 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 60 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 364c331..5311b0d 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -66,7 +66,7 @@ config TPM_ON_FAST_SPI
 
 config SOC_INTEL_COMMON_RESET
 	bool
-	default y
+	default n
 
 config MMCONF_BASE_ADDRESS
 	hex "PCI MMIO Base Address"
diff --git a/src/soc/intel/apollolake/reset.c b/src/soc/intel/apollolake/reset.c
index 644d88d..ab7c15a 100644
--- a/src/soc/intel/apollolake/reset.c
+++ b/src/soc/intel/apollolake/reset.c
@@ -2,6 +2,8 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2016 Intel Corporation.
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014-2016 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -13,11 +15,68 @@
  * GNU General Public License for more details.
  */
 
+#include <arch/hlt.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <halt.h>
 #include <reset.h>
+#include <soc/heci.h>
 #include <soc/pm.h>
+#include <soc/pci_devs.h>
+
+/* Reset control port */
+#define RST_CNT			0xcf9
+#define FULL_RST		(1 << 3)
+#define RST_CPU			(1 << 2)
+#define SYS_RST			(1 << 1)
+
+static void reset_common(void)
+{
+	printk(BIOS_DEBUG, "resetting..\n");
+
+	if (!heci_cse_normal()) {
+		printk(BIOS_DEBUG, "CSE is not in normal state, resetting\n");
+		return;
+	}
+
+	if (!heci_cse_done()) {
+		uint64_t spins = 0;
+		printk(BIOS_DEBUG, "CSE is not done, spinning\n");
+		while (!heci_cse_done())
+			spins++;
+		printk(BIOS_DEBUG, "CSE is ready, spin count %llu\n", spins);
+	}
+}
 
 void global_reset(void)
 {
 	global_reset_enable(1);
 	hard_reset();
 }
+
+void hard_reset(void)
+{
+	reset_common();
+	/* S0->S5->S0 trip. */
+	outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT);
+	while (1)
+		hlt();
+}
+
+void soft_reset(void)
+{
+	reset_common();
+	/* PMC_PLTRST# asserted. */
+	outb(RST_CPU | SYS_RST, RST_CNT);
+	while (1)
+		hlt();
+}
+
+void cpu_reset(void)
+{
+	reset_common();
+	/* Sends INIT# to CPU */
+	outb(RST_CPU, RST_CNT);
+	while (1)
+		hlt();
+}