[coreboot-gerrit] Patch set updated for coreboot: soc/intel/skylake: use common Intel ACPI hardware definitions
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Thu Jul 14 21:15:03 CEST 2016
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15671
-gerrit
commit 37a79965281d1d3c6de2aa65e6988e5269bc6523
Author: Aaron Durbin <adurbin at chromium.org>
Date: Wed Jul 13 23:20:51 2016 -0500
soc/intel/skylake: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: I5f2aa424a167092b570fda020cddce5ef906860a
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/soc/intel/skylake/Kconfig | 1 +
src/soc/intel/skylake/elog.c | 4 ++--
src/soc/intel/skylake/include/soc/pm.h | 13 +------------
src/soc/intel/skylake/pmc.c | 2 +-
src/soc/intel/skylake/romstage/power_state.c | 24 +++++++++++-------------
src/soc/intel/skylake/smihandler.c | 18 +++++++++---------
6 files changed, 25 insertions(+), 37 deletions(-)
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 6843cef..0871ed0 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -7,6 +7,7 @@ if SOC_INTEL_SKYLAKE
config CPU_SPECIFIC_OPTIONS
def_bool y
+ select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ARCH_BOOTBLOCK_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c
index fc3e29a..ca6455e 100644
--- a/src/soc/intel/skylake/elog.c
+++ b/src/soc/intel/skylake/elog.c
@@ -83,7 +83,7 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps)
elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
/* TCO Timeout */
- if (ps->prev_sleep_state != 3 &&
+ if (ps->prev_sleep_state != ACPI_S3 &&
ps->tco2_sts & TCO2_STS_SECOND_TO)
elog_add_event(ELOG_TYPE_TCO_RESET);
@@ -100,7 +100,7 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps)
elog_add_event(ELOG_TYPE_SYSTEM_RESET);
/* ACPI Wake Event */
- if (ps->prev_sleep_state != SLEEP_STATE_S0)
+ if (ps->prev_sleep_state != ACPI_S0)
elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state);
}
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h
index a89b764..d1aa0b4 100644
--- a/src/soc/intel/skylake/include/soc/pm.h
+++ b/src/soc/intel/skylake/include/soc/pm.h
@@ -17,6 +17,7 @@
#ifndef _SOC_PM_H_
#define _SOC_PM_H_
+#include <arch/acpi.h>
#include <arch/io.h>
#include <soc/pmc.h>
@@ -38,14 +39,6 @@
#define GBL_EN (1 << 5)
#define TMROF_EN (1 << 0)
#define PM1_CNT 0x04
-#define SLP_EN (1 << 13)
-#define SLP_TYP (7 << 10)
-#define SLP_TYP_SHIFT 10
-#define SLP_TYP_S0 0
-#define SLP_TYP_S1 1
-#define SLP_TYP_S3 5
-#define SLP_TYP_S4 6
-#define SLP_TYP_S5 7
#define GBL_RLS (1 << 2)
#define BM_RLD (1 << 1)
#define SCI_EN (1 << 0)
@@ -141,10 +134,6 @@
#define MAINBOARD_POWER_ON 1
#define MAINBOARD_POWER_KEEP 2
-#define SLEEP_STATE_S0 0
-#define SLEEP_STATE_S3 3
-#define SLEEP_STATE_S5 5
-
struct chipset_power_state {
uint16_t pm1_sts;
uint16_t pm1_en;
diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c
index eb7a160..6b7a17b 100644
--- a/src/soc/intel/skylake/pmc.c
+++ b/src/soc/intel/skylake/pmc.c
@@ -101,7 +101,7 @@ static void pch_pmc_read_resources(device_t dev)
static void pch_set_acpi_mode(void)
{
- if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && acpi_slp_type != 3) {
+ if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) {
printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_DISABLE, APM_CNT);
printk(BIOS_DEBUG, "done.\n");
diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c
index 85234b5..209beeb 100644
--- a/src/soc/intel/skylake/romstage/power_state.c
+++ b/src/soc/intel/skylake/romstage/power_state.c
@@ -54,17 +54,16 @@ ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state)
static uint32_t prev_sleep_state(struct chipset_power_state *ps)
{
/* Default to S0. */
- uint32_t prev_sleep_state = SLEEP_STATE_S0;
+ uint32_t prev_sleep_state = ACPI_S0;
if (ps->pm1_sts & WAK_STS) {
- switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
- case SLP_TYP_S3:
- prev_sleep_state = SLEEP_STATE_S3;
+ switch (acpi_sleep_from_pm1(ps->pm1_cnt)) {
+ case ACPI_S3:
+ if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
+ prev_sleep_state = ACPI_S3;
break;
-#endif
- case SLP_TYP_S5:
- prev_sleep_state = SLEEP_STATE_S5;
+ case ACPI_S5:
+ prev_sleep_state = ACPI_S5;
break;
}
/* Clear SLP_TYP. */
@@ -76,7 +75,7 @@ static uint32_t prev_sleep_state(struct chipset_power_state *ps)
* from a true G3 state.
*/
if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))
- prev_sleep_state = SLEEP_STATE_S5;
+ prev_sleep_state = ACPI_S5;
}
/*
@@ -84,7 +83,7 @@ static uint32_t prev_sleep_state(struct chipset_power_state *ps)
* need to check both deep sleep well and normal suspend well.
* Otherwise just check deep sleep well.
*/
- if (prev_sleep_state == SLEEP_STATE_S3) {
+ if (prev_sleep_state == ACPI_S3) {
/* PWR_FLR represents deep sleep power well loss. */
uint32_t mask = PWR_FLR;
@@ -93,7 +92,7 @@ static uint32_t prev_sleep_state(struct chipset_power_state *ps)
mask |= SUS_PWR_FLR;
if (ps->gen_pmcon_b & mask)
- prev_sleep_state = SLEEP_STATE_S5;
+ prev_sleep_state = ACPI_S5;
}
return prev_sleep_state;
@@ -163,8 +162,7 @@ struct chipset_power_state *fill_power_state(void)
int vboot_platform_is_resuming(void)
{
- int typ = (inl(ACPI_BASE_ADDRESS + PM1_CNT) & SLP_TYP) >> SLP_TYP_SHIFT;
- return typ == SLP_TYP_S3;
+ return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3;
}
/*
diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c
index c5e6c82..1834815 100644
--- a/src/soc/intel/skylake/smihandler.c
+++ b/src/soc/intel/skylake/smihandler.c
@@ -129,34 +129,34 @@ static void southbridge_smi_sleep(void)
/* Figure out SLP_TYP */
reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT);
printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
- slp_typ = (reg32 >> 10) & 7;
+ slp_typ = acpi_sleep_from_pm1(reg32);
/* Do any mainboard sleep handling */
- mainboard_smi_sleep(slp_typ-2);
+ mainboard_smi_sleep(slp_typ);
if (IS_ENABLED(CONFIG_ELOG_GSMI))
/* Log S3, S4, and S5 entry */
- if (slp_typ >= 5)
- elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2);
+ if (slp_typ >= ACPI_S3)
+ elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
/* Clear pending GPE events */
clear_gpe_status();
/* Next, do the deed. */
switch (slp_typ) {
- case SLP_TYP_S0:
+ case ACPI_S0:
printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n");
break;
- case SLP_TYP_S1:
+ case ACPI_S1:
printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n");
break;
- case SLP_TYP_S3:
+ case ACPI_S3:
printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
/* Invalidate the cache before going to S3 */
wbinvd();
break;
- case SLP_TYP_S5:
+ case ACPI_S5:
printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
/*TODO: cmos_layout.bin need to verify; cause wrong CMOS setup*/
s5pwr = MAINBOARD_POWER_ON;
@@ -190,7 +190,7 @@ static void southbridge_smi_sleep(void)
enable_pm1_control(SLP_EN);
/* Make sure to stop executing code here for S3/S4/S5 */
- if (slp_typ > 1)
+ if (slp_typ >= ACPI_S3)
hlt();
/*
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