[coreboot-gerrit] Patch set updated for coreboot: rockchip/rk3399: extend romstage range

Martin Roth (martinroth@google.com) gerrit at coreboot.org
Thu Jul 14 20:04:05 CEST 2016


Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15660

-gerrit

commit ddd31173ba4bbdd3f724f043ec20afae5159dbc2
Author: Lin Huang <hl at rock-chips.com>
Date:   Mon Jul 11 16:48:17 2016 +0800

    rockchip/rk3399: extend romstage range
    
    rk3399 sdram size is 192K, and there still some unused space.
    We need more romstage space to include the sdram config, so extend
    the romstage range.
    
    BRANCH=none
    BUG=chrome-os-partner:54871
    TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass
    
    Change-Id: Ib827345fe646e985773e6ce3e98ac3f64317fffb
    Signed-off-by: Martin Roth <martinroth at chromium.org>
    Original-Commit-Id: 626ab15bb4ebb004d5294b948bbdecc77a72a484
    Original-Change-Id: Ib5aa1e1b942cde8d9476773f5a84ac70bb830c80
    Original-Signed-off-by: Lin Huang <hl at rock-chips.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/359092
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
---
 src/soc/rockchip/rk3399/include/soc/memlayout.ld | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
index 0ad9939..96dd108 100644
--- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
@@ -28,10 +28,10 @@ SECTIONS
 	BOOTBLOCK(0xFF8C2004, 31K - 4)
 	PRERAM_CBMEM_CONSOLE(0xFF8C9C00, 5K)
 	PRERAM_CBFS_CACHE(0xFF8CB000, 4K)
-	OVERLAP_VERSTAGE_ROMSTAGE(0xFF8CC000, 64K)
-	VBOOT2_WORK(0XFF8DC000, 12K)
-	TTB(0xFF8DF000, 32K)
-	TIMESTAMP(0xFF8E7000, 1K)
-	STACK(0xFF8E7400, 24K)
+	TTB(0xFF8CC000, 32K)
+	OVERLAP_VERSTAGE_ROMSTAGE(0xFF8D4000, 75K)
+	VBOOT2_WORK(0XFF8E6C00, 12K)
+	TIMESTAMP(0xFF8E9C00, 1K)
+	STACK(0xFF8EA000, 24K)
 	SRAM_END(0xFF8F0000)
 }



More information about the coreboot-gerrit mailing list