[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: provide poweroff() implementation

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15686

-gerrit

commit 6de8f4c0f259ae3682ce7c1c411a186f9b5022ae
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Jul 14 00:26:50 2016 -0500

    soc/intel/apollolake: provide poweroff() implementation
    
    Implement poweroff() by putting the chipset into ACPI S5 state.
    
    BUG=chrome-os-partner:54977
    
    Change-Id: I4ee269f03afd252d4bce909a8cc7c64d6270b16e
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/apollolake/pmutil.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index 874d9ad..6a58220 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -26,6 +26,7 @@
 #include <soc/pm.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <reset.h>
 #include <vendorcode/google/chromeos/vboot_common.h>
 
 static uintptr_t read_pmc_mmio_bar(void)
@@ -413,3 +414,8 @@ void vboot_platform_prepare_reboot(void)
 	const uint16_t port = ACPI_PMIO_BASE + PM1_CNT;
 	outl((inl(port) & ~(SLP_TYP)) | (SLP_TYP_S5 << SLP_TYP_SHIFT), port);
 }
+
+void poweroff(void)
+{
+	enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
+}