[coreboot-gerrit] Patch set updated for coreboot: AGESA: Use common romstage ram stack

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15466

-gerrit

commit 3ae520bd536b0da8f2996fc0bb815e319e22bd43
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Mon Jun 27 16:15:02 2016 +0300

    AGESA: Use common romstage ram stack
    
    Change-Id: Ie120360fa79aa0f6f6d82606838404bb0b0d9681
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/cpu/amd/agesa/s3_resume.c      | 8 +++++---
 src/lib/Makefile.inc               | 1 +
 src/northbridge/amd/agesa/oem_s3.c | 4 ++--
 3 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c
index 54e41c1..e74c5b3 100644
--- a/src/cpu/amd/agesa/s3_resume.c
+++ b/src/cpu/amd/agesa/s3_resume.c
@@ -21,18 +21,20 @@
 #include <cpu/amd/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cbmem.h>
+#include <program_loading.h>
 #include <string.h>
 #include <halt.h>
 #include "s3_resume.h"
 
 static void move_stack_high_mem(void)
 {
-	void *high_stack = cbmem_find(CBMEM_ID_ROMSTAGE_RAM_STACK);
-	if (high_stack == NULL)
+	uintptr_t high_stack = romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE,
+		ROMSTAGE_STACK_CBMEM);
+	if (!high_stack)
 		halt();
 
 	/* TODO: Make the switch with empty stack instead. */
-	memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE);
+	memcpy((void*)high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE);
 
 	/* TODO: We only switch stack on BSP. */
 #ifdef __x86_64__
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 5a8f77f..1850341 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -81,6 +81,7 @@ ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c
 romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c
 romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
 romstage-y += romstage_stack.c
+ramstage-y += romstage_stack.c
 romstage-y += stack.c
 ramstage-y += rtc.c
 
diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c
index 8cce0e7..4f2788e 100644
--- a/src/northbridge/amd/agesa/oem_s3.c
+++ b/src/northbridge/amd/agesa/oem_s3.c
@@ -17,6 +17,7 @@
 #include <spi_flash.h>
 #include <string.h>
 #include <cbmem.h>
+#include <program_loading.h>
 #include <cpu/amd/agesa/s3_resume.h>
 #include <northbridge/amd/agesa/agesawrapper.h>
 #include <AGESA.h>
@@ -119,8 +120,7 @@ AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams)
 	u32 MTRRStorageSize = 0;
 	uintptr_t pos, size;
 
-	if (HIGH_ROMSTAGE_STACK_SIZE)
-		cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, HIGH_ROMSTAGE_STACK_SIZE);
+	romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE, ROMSTAGE_STACK_CBMEM);
 
 	/* To be consumed in AmdInitResume. */
 	get_s3nv_data(S3DataTypeNonVolatile, &pos, &size);