[coreboot-gerrit] Patch set updated for coreboot: southbridge/intel/ibexpeak: use common Intel ACPI hardware definitions

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15677

-gerrit

commit cdb726a638a8611584e7632a0fb15ba502984b14
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Jul 13 23:23:54 2016 -0500

    southbridge/intel/ibexpeak: use common Intel ACPI hardware definitions
    
    Transition to using the common Intel ACPI hardware definitions
    generic ACPI definitions.
    
    BUG=chrome-os-partner:54977
    
    Change-Id: I65270ddcb612f9c63d7dbb2409e4395f96e10a51
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/southbridge/intel/ibexpeak/Kconfig      |  1 +
 src/southbridge/intel/ibexpeak/pch.h        |  9 ++-------
 src/southbridge/intel/ibexpeak/smihandler.c | 27 +++++++++++++--------------
 3 files changed, 16 insertions(+), 21 deletions(-)

diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig
index f12068c..ad32a9b 100644
--- a/src/southbridge/intel/ibexpeak/Kconfig
+++ b/src/southbridge/intel/ibexpeak/Kconfig
@@ -20,6 +20,7 @@ if SOUTHBRIDGE_INTEL_IBEXPEAK
 
 config SOUTH_BRIDGE_OPTIONS # dummy
 	def_bool y
+	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select IOAPIC
 	select HAVE_HARD_RESET
 	select HAVE_USBDEBUG
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index 07127fa..6c694fd 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -17,6 +17,8 @@
 #ifndef SOUTHBRIDGE_INTEL_BD82X6X_PCH_H
 #define SOUTHBRIDGE_INTEL_BD82X6X_PCH_H
 
+#include <arch/acpi.h>
+
 /* PCH types */
 #define PCH_TYPE_CPT	   0x1c /* CougarPoint */
 #define PCH_TYPE_PPT	   0x1e /* IvyBridge */
@@ -449,13 +451,6 @@ void southbridge_configure_default_intmap(void);
 #define   GBL_EN	(1 << 5)
 #define   TMROF_EN	(1 << 0)
 #define PM1_CNT		0x04
-#define   SLP_EN	(1 << 13)
-#define   SLP_TYP	(7 << 10)
-#define    SLP_TYP_S0	0
-#define    SLP_TYP_S1	1
-#define    SLP_TYP_S3	5
-#define    SLP_TYP_S4	6
-#define    SLP_TYP_S5	7
 #define   GBL_RLS	(1 << 2)
 #define   BM_RLD	(1 << 1)
 #define   SCI_EN	(1 << 0)
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index 319f994..6a48277 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -363,8 +363,8 @@ static void xhci_sleep(u8 slp_typ)
 	u16 reg16;
 
 	switch (slp_typ) {
-	case SLP_TYP_S3:
-	case SLP_TYP_S4:
+	case ACPI_S3:
+	case ACPI_S4:
 		reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74);
 		reg16 &= ~0x03UL;
 		pci_write_config32(PCH_XHCI_DEV, 0x74, reg16);
@@ -394,7 +394,7 @@ static void xhci_sleep(u8 slp_typ)
 		pci_write_config16(PCH_XHCI_DEV, 0x74, reg16);
 		break;
 
-	case SLP_TYP_S5:
+	case ACPI_S5:
 		reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74);
 		reg16 |= ((1 << 8) | 0x03);
 		pci_write_config16(PCH_XHCI_DEV, 0x74, reg16);
@@ -402,7 +402,6 @@ static void xhci_sleep(u8 slp_typ)
 	}
 }
 
-
 static void southbridge_smi_sleep(void)
 {
 	u8 reg8;
@@ -426,27 +425,27 @@ static void southbridge_smi_sleep(void)
 	/* Figure out SLP_TYP */
 	reg32 = inl(pmbase + PM1_CNT);
 	printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
-	slp_typ = (reg32 >> 10) & 7;
+	slp_typ = acpi_sleep_from_pm1(reg32);
 
 	if (smm_get_gnvs()->xhci)
 		xhci_sleep(slp_typ);
 
 	/* Do any mainboard sleep handling */
-	mainboard_smi_sleep(slp_typ-2);
+	mainboard_smi_sleep(slp_typ);
 
 #if CONFIG_ELOG_GSMI
 	/* Log S3, S4, and S5 entry */
-	if (slp_typ >= 5)
-		elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2);
+	if (slp_typ >= ACPI_S3)
+		elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
 #endif
 
 	/* Next, do the deed.
 	 */
 
 	switch (slp_typ) {
-	case 0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;
-	case 1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;
-	case 5:
+	case ACPI_S0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;
+	case ACPI_S1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;
+	case ACPI_S3:
 		printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
 
 		/* Gate memory reset */
@@ -455,8 +454,8 @@ static void southbridge_smi_sleep(void)
 		/* Invalidate the cache before going to S3 */
 		wbinvd();
 		break;
-	case 6: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
-	case 7:
+	case ACPI_S4: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
+	case ACPI_S5:
 		printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
 
 		outl(0, pmbase + GPE0_EN);
@@ -485,7 +484,7 @@ static void southbridge_smi_sleep(void)
 	outl(reg32 | SLP_EN, pmbase + PM1_CNT);
 
 	/* Make sure to stop executing code here for S3/S4/S5 */
-	if (slp_typ > 1)
+	if (slp_typ >= ACPI_S3)
 		halt();
 
 	/* In most sleep states, the code flow of this function ends at