[coreboot-gerrit] Patch set updated for coreboot: soc/intel/baytrail: use common Intel ACPI hardware definitions
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Thu Jul 14 09:03:15 CEST 2016
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15669
-gerrit
commit 0ce15ce7ea2a8f617d1aefb57b2a72e7bed54bf6
Author: Aaron Durbin <adurbin at chromium.org>
Date: Wed Jul 13 23:20:07 2016 -0500
soc/intel/baytrail: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: Idf055fa86b56001a805e139de6723dfb77dcb224
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/soc/intel/baytrail/Kconfig | 1 +
src/soc/intel/baytrail/include/soc/pmc.h | 9 +--------
src/soc/intel/baytrail/romstage/raminit.c | 7 ++++---
src/soc/intel/baytrail/romstage/romstage.c | 23 +++++++++++------------
src/soc/intel/baytrail/smihandler.c | 20 ++++++++++----------
5 files changed, 27 insertions(+), 33 deletions(-)
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index df8765d..d58d4dd 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -7,6 +7,7 @@ if SOC_INTEL_BAYTRAIL
config CPU_SPECIFIC_OPTIONS
def_bool y
+ select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
diff --git a/src/soc/intel/baytrail/include/soc/pmc.h b/src/soc/intel/baytrail/include/soc/pmc.h
index d61b700..c8d6a67 100644
--- a/src/soc/intel/baytrail/include/soc/pmc.h
+++ b/src/soc/intel/baytrail/include/soc/pmc.h
@@ -16,6 +16,7 @@
#ifndef _BAYTRAIL_PMC_H_
#define _BAYTRAIL_PMC_H_
+#include <arch/acpi.h>
#define IOCOM1 0x3f8
@@ -147,14 +148,6 @@
#define GBL_EN (1 << 5)
#define TMROF_EN (1 << 0)
#define PM1_CNT 0x04
-#define SLP_EN (1 << 13)
-#define SLP_TYP_SHIFT 10
-#define SLP_TYP (7 << SLP_TYP_SHIFT)
-#define SLP_TYP_S0 0
-#define SLP_TYP_S1 1
-#define SLP_TYP_S3 5
-#define SLP_TYP_S4 6
-#define SLP_TYP_S5 7
#define GBL_RLS (1 << 2)
#define BM_RLD (1 << 1)
#define SCI_EN (1 << 0)
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index 0784f69..d45b9ea 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -14,6 +14,7 @@
*/
#include <stddef.h>
+#include <arch/acpi.h>
#include <arch/io.h>
#include <bootmode.h>
#include <cbfs.h>
@@ -127,7 +128,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
} else if (!mrc_cache_get_current(&cache)) {
mp->saved_data_size = cache->size;
mp->saved_data = &cache->data[0];
- } else if (prev_sleep_state == 3) {
+ } else if (prev_sleep_state == ACPI_S3) {
/* If waking from S3 and no cache then. */
printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n");
post_code(POST_RESUME_FAILURE);
@@ -135,7 +136,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
} else {
printk(BIOS_DEBUG, "No MRC cache found.\n");
#if CONFIG_EC_GOOGLE_CHROMEEC
- if (prev_sleep_state == 0) {
+ if (prev_sleep_state == ACPI_S0) {
/* Ensure EC is running RO firmware. */
google_chromeec_check_ec_image(EC_IMAGE_RO);
}
@@ -162,7 +163,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
print_dram_info();
- if (prev_sleep_state != 3) {
+ if (prev_sleep_state != ACPI_S3) {
cbmem_initialize_empty();
} else if (cbmem_initialize()) {
#if CONFIG_HAVE_ACPI_RESUME
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index d7e8b17..96ae86d 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -184,17 +184,16 @@ static struct chipset_power_state *fill_power_state(void)
static int chipset_prev_sleep_state(struct chipset_power_state *ps)
{
/* Default to S0. */
- int prev_sleep_state = 0;
+ int prev_sleep_state = ACPI_S0;
if (ps->pm1_sts & WAK_STS) {
- switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
- #if CONFIG_HAVE_ACPI_RESUME
- case SLP_TYP_S3:
- prev_sleep_state = 3;
+ switch (acpi_sleep_from_pm1(ps->pm1_cnt)) {
+ case ACPI_S3:
+ if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
+ prev_sleep_state = ACPI_S3;
break;
- #endif
- case SLP_TYP_S5:
- prev_sleep_state = 5;
+ case ACPI_S5:
+ prev_sleep_state = ACPI_S5;
break;
}
/* Clear SLP_TYP. */
@@ -202,7 +201,7 @@ static int chipset_prev_sleep_state(struct chipset_power_state *ps)
}
if (ps->gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) {
- prev_sleep_state = 5;
+ prev_sleep_state = ACPI_S5;
}
return prev_sleep_state;
@@ -223,7 +222,7 @@ void romstage_common(struct romstage_params *params)
printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state);
#if CONFIG_ELOG_BOOT_COUNT
- if (prev_sleep_state != 3)
+ if (prev_sleep_state != ACPI_S3)
boot_count_increment();
#endif
@@ -235,12 +234,12 @@ void romstage_common(struct romstage_params *params)
handoff = romstage_handoff_find_or_add();
if (handoff != NULL)
- handoff->s3_resume = (prev_sleep_state == 3);
+ handoff->s3_resume = (prev_sleep_state == ACPI_S3);
else
printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
if (IS_ENABLED(CONFIG_LPC_TPM)) {
- init_tpm(prev_sleep_state == 3);
+ init_tpm(prev_sleep_state == ACPI_S3);
}
}
diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c
index 0e1094e..1e8c8e0 100644
--- a/src/soc/intel/baytrail/smihandler.c
+++ b/src/soc/intel/baytrail/smihandler.c
@@ -107,37 +107,37 @@ static void southbridge_smi_sleep(void)
/* Figure out SLP_TYP */
reg32 = inl(pmbase + PM1_CNT);
printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
- slp_typ = (reg32 >> 10) & 7;
+ slp_typ = acpi_sleep_from_pm1(reg32);
/* Do any mainboard sleep handling */
- mainboard_smi_sleep(slp_typ-2);
+ mainboard_smi_sleep(slp_typ);
#if CONFIG_ELOG_GSMI
/* Log S3, S4, and S5 entry */
- if (slp_typ >= 5)
- elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2);
+ if (slp_typ >= ACPI_S3)
+ elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
#endif
/* Next, do the deed.
*/
switch (slp_typ) {
- case SLP_TYP_S0:
+ case ACPI_S0:
printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n");
break;
- case SLP_TYP_S1:
+ case ACPI_S1:
printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n");
break;
- case SLP_TYP_S3:
+ case ACPI_S3:
printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
/* Invalidate the cache before going to S3 */
wbinvd();
break;
- case SLP_TYP_S4:
+ case ACPI_S4:
printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n");
break;
- case SLP_TYP_S5:
+ case ACPI_S5:
printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
/* Disable all GPE */
@@ -158,7 +158,7 @@ static void southbridge_smi_sleep(void)
enable_pm1_control(SLP_EN);
/* Make sure to stop executing code here for S3/S4/S5 */
- if (slp_typ > 1)
+ if (slp_typ > ACPI_S3)
halt();
/* In most sleep states, the code flow of this function ends at
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