[coreboot-gerrit] Patch set updated for coreboot: drivers/intel/fsp1_1: align on using ACPI_Sx definitions

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15665

-gerrit

commit 6ba74d235a6a42833aa9e65e62aa1da33e0ea4dc
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Jul 13 23:09:52 2016 -0500

    drivers/intel/fsp1_1: align on using ACPI_Sx definitions
    
    The SLEEP_STATE_x definitions in the chipsets utilizing
    FSP 1.1. driver have the exact same values as the ACPI_Sx
    definitions. The chipsets will be moved over subsequently,
    but updating this first allows the per-chipset patches
    to be isolated.
    
    BUG=chrome-os-partner:54977
    
    Change-Id: I383a9a732ef68bf2276f6149ffa5360bcdfb70b3
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/drivers/intel/fsp1_1/raminit.c  |  5 +++--
 src/drivers/intel/fsp1_1/romstage.c | 13 +++++++------
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
index e505b93..3eee2da 100644
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <arch/acpi.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <fsp/memmap.h>
@@ -80,7 +81,7 @@ void raminit(struct romstage_params *params)
 	/* Zero fill RT Buffer data and start populating fields. */
 	memset(&fsp_rt_common_buffer, 0, sizeof(fsp_rt_common_buffer));
 	pei_ptr = params->pei_data;
-	if (pei_ptr->boot_mode == SLEEP_STATE_S3) {
+	if (pei_ptr->boot_mode == ACPI_S3) {
 		fsp_rt_common_buffer.BootMode = BOOT_ON_S3_RESUME;
 	} else if (pei_ptr->saved_data != NULL) {
 		fsp_rt_common_buffer.BootMode =
@@ -156,7 +157,7 @@ void raminit(struct romstage_params *params)
 
 	/* Migrate CAR data */
 	printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top());
-	if (pei_ptr->boot_mode != SLEEP_STATE_S3) {
+	if (pei_ptr->boot_mode != ACPI_S3) {
 		cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
 			fsp_reserved_bytes);
 	} else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index f99c87a..c1b1ca5 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -15,6 +15,7 @@
  */
 
 #include <stddef.h>
+#include <arch/acpi.h>
 #include <arch/io.h>
 #include <arch/cbfs.h>
 #include <arch/early_variables.h>
@@ -109,7 +110,7 @@ void romstage_common(struct romstage_params *params)
 	pei_data->boot_mode = params->power_state->prev_sleep_state;
 
 #if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
-	if (params->power_state->prev_sleep_state != SLEEP_STATE_S3)
+	if (params->power_state->prev_sleep_state != ACPI_S3)
 		boot_count_increment();
 #endif
 
@@ -131,7 +132,7 @@ void romstage_common(struct romstage_params *params)
 			/* MRC cache found */
 			params->pei_data->saved_data_size = cache->size;
 			params->pei_data->saved_data = &cache->data[0];
-		} else if (params->pei_data->boot_mode == SLEEP_STATE_S3) {
+		} else if (params->pei_data->boot_mode == ACPI_S3) {
 			/* Waking from S3 and no cache. */
 			printk(BIOS_DEBUG,
 			       "No MRC cache found in S3 resume path.\n");
@@ -151,7 +152,7 @@ void romstage_common(struct romstage_params *params)
 	if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) {
 		printk(BIOS_DEBUG, "MRC data at %p %d bytes\n",
 			pei_data->data_to_save, pei_data->data_to_save_size);
-		if ((params->pei_data->boot_mode != SLEEP_STATE_S3)
+		if ((params->pei_data->boot_mode != ACPI_S3)
 			&& (params->pei_data->data_to_save_size != 0)
 			&& (params->pei_data->data_to_save != NULL))
 				mrc_cache_stash_data_with_version(
@@ -167,7 +168,7 @@ void romstage_common(struct romstage_params *params)
 	handoff = romstage_handoff_find_or_add();
 	if (handoff != NULL)
 		handoff->s3_resume = (params->power_state->prev_sleep_state ==
-				      SLEEP_STATE_S3);
+				      ACPI_S3);
 	else {
 		printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
 		hard_reset();
@@ -181,7 +182,7 @@ void romstage_common(struct romstage_params *params)
 	    !IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) &&
 	    !IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK))
 		init_tpm(params->power_state->prev_sleep_state ==
-			 SLEEP_STATE_S3);
+			 ACPI_S3);
 }
 
 void after_cache_as_ram_stage(void)
@@ -204,7 +205,7 @@ __attribute__((weak)) void mainboard_check_ec_image(
 	struct pei_data *pei_data;
 
 	pei_data = params->pei_data;
-	if (params->pei_data->boot_mode == SLEEP_STATE_S0) {
+	if (params->pei_data->boot_mode == ACPI_S0) {
 		/* Ensure EC is running RO firmware. */
 		google_chromeec_check_ec_image(EC_IMAGE_RO);
 	}