[coreboot-gerrit] New patch to review for coreboot: soc/intel/apollolake: use common Intel ACPI hardware definitions

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15667

-gerrit

commit 38dc56ba3dd5fe34f1ec65f52fff40062e078227
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Jul 13 23:17:38 2016 -0500

    soc/intel/apollolake: use common Intel ACPI hardware definitions
    
    Transition to using the common Intel ACPI hardware definitions
    generic ACPI definitions.
    
    BUG=chrome-os-partner:54977
    
    Change-Id: Icaca9367b526999f0475b21dd968724baa32e3f6
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/apollolake/Kconfig          |  1 +
 src/soc/intel/apollolake/include/soc/pm.h | 13 +------------
 src/soc/intel/apollolake/pmutil.c         | 15 +++++++--------
 src/soc/intel/apollolake/romstage.c       |  8 ++++----
 4 files changed, 13 insertions(+), 24 deletions(-)

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 364c331..d36fc06 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -7,6 +7,7 @@ if SOC_INTEL_APOLLOLAKE
 
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
+	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	select ARCH_BOOTBLOCK_X86_32
 	select ARCH_RAMSTAGE_X86_32
 	select ARCH_ROMSTAGE_X86_32
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index b0e2da2..d8eb50b 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -19,6 +19,7 @@
 #define _SOC_APOLLOLAKE_PM_H_
 
 #include <stdint.h>
+#include <arch/acpi.h>
 
 /* ACPI_BASE_ADDRESS */
 
@@ -35,13 +36,6 @@
 #define   TMROF_EN      	(1 << 0)
 
 #define PM1_CNT			0x04
-#define   SLP_EN		(1 << 13)
-#define   SLP_TYP_SHIFT		10
-#define   SLP_TYP		(7 << SLP_TYP_SHIFT)
-#define    SLP_TYP_S0		0
-#define    SLP_TYP_S3		5
-#define    SLP_TYP_S4		6
-#define    SLP_TYP_S5		7
 #define   SCI_EN		(1 << 0)
 
 #define PM1_TMR			0x08
@@ -151,11 +145,6 @@
 #define  PMC_GPE_N_63_32	7
 #define  PMC_GPE_W_31_0		9
 
-/* Generic sleep state types */
-#define SLEEP_STATE_S0		0
-#define SLEEP_STATE_S3		3
-#define SLEEP_STATE_S5		5
-
 /* Track power state from reset to log events. */
 struct chipset_power_state {
 	uint16_t pm1_sts;
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index f25adfb..f1888cb 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -307,17 +307,16 @@ void clear_pmc_status(void)
 int chipset_prev_sleep_state(struct chipset_power_state *ps)
 {
 	/* Default to S0. */
-	int prev_sleep_state = SLEEP_STATE_S0;
+	int prev_sleep_state = ACPI_S0;
 
 	if (ps->pm1_sts & WAK_STS) {
-		switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
-		case SLP_TYP_S3:
-			prev_sleep_state = SLEEP_STATE_S3;
+		switch (acpi_sleep_from_pm1(ps->pm1_cnt)) {
+		case ACPI_S3:
+			if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
+				prev_sleep_state = ACPI_S3;
 			break;
-#endif
-		case SLP_TYP_S5:
-			prev_sleep_state = SLEEP_STATE_S5;
+		case ACPI_S5:
+			prev_sleep_state = ACPI_S5;
 			break;
 		}
 
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 049bf4f..90b8cf1 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -136,7 +136,7 @@ asmlinkage void car_stage_entry(void)
 	fsp_find_reserved_memory(&fsp_mem, hob_list_ptr);
 
 	/* initialize cbmem by adding FSP reserved memory first thing */
-	if (prev_sleep_state != SLEEP_STATE_S3) {
+	if (prev_sleep_state != ACPI_S3) {
 		cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
 			range_entry_size(&fsp_mem));
 	} else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
@@ -158,7 +158,7 @@ asmlinkage void car_stage_entry(void)
 
 	/* Save MRC Data to CBMEM */
 	if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS) &&
-	    (prev_sleep_state != SLEEP_STATE_S3))
+	    (prev_sleep_state != ACPI_S3))
 	{
 		mrc_data = fsp_find_nv_storage_data(&mrc_data_size);
 		if (mrc_data && mrc_cache_stash_data(mrc_data, mrc_data_size) < 0)
@@ -168,7 +168,7 @@ asmlinkage void car_stage_entry(void)
 	/* Create romstage handof information */
 	handoff = romstage_handoff_find_or_add();
 	if (handoff != NULL)
-		handoff->s3_resume = (prev_sleep_state == SLEEP_STATE_S3);
+		handoff->s3_resume = (prev_sleep_state == ACPI_S3);
 	else
 		printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
 
@@ -233,7 +233,7 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd)
 			/* MRC cache found */
 			arch_upd->NvsBufferPtr = (void *)mrc_cache->data;
 			arch_upd->BootMode =
-				prev_sleep_state == SLEEP_STATE_S3 ?
+				prev_sleep_state == ACPI_S3 ?
 				FSP_BOOT_ON_S3_RESUME:
 				FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;
 			printk(BIOS_DEBUG, "MRC cache found, size %x bootmode:%d\n",