[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/apollolake: add initial ITSS support

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 1318e88352d7b20661adec82769f46308471d739
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Jul 12 23:39:51 2016 -0500

    soc/intel/apollolake: add initial ITSS support
    
    The interrupt and timer subsystem (ITSS) sits between the APIC
    and the other logic blocks. It only supports positive polarity
    events, but there's a polarity inversion setting for each IRQ such
    that it can pass the signal on to the APIC according to the
    expected APIC redirection entry values. This support is needed
    in order for the platform/board to set the expected interrupt
    polarity into the APIC for gpio signals.
    
    BUG=chrome-os-partner:54955
    
    Change-Id: I50ea1b7c4a7601e760878af515518cc0e808c0d1
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: https://review.coreboot.org/15647
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Andrey Petrov <andrey.petrov at intel.com>
    Reviewed-by: Furquan Shaikh <furquan at google.com>


See https://review.coreboot.org/15647 for details.

-gerrit