[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: add offset of GPIO_TIER1_SCI_EN bit

[Shaunak Saha (shaunak.saha@intel.com)]

Shaunak Saha (shaunak.saha at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15612

-gerrit

commit 6cf92364127471f2d172f07414e6a26d797743ee
Author: Shaunak Saha <shaunak.saha at intel.com>
Date:   Mon Jul 11 16:03:52 2016 -0700

    soc/intel/apollolake: add offset of GPIO_TIER1_SCI_EN bit
    
    This patch adds the support for gpio_tier1_sci_en bit which
    needs to be set before going to sleep so that when
    gpio_tier1_sci_sts bit gets set platform can wake
    from S3.
    
    BUG = chrome-os-partner:53992
    TEST = Platform wakes from S3 on lidopen,key press.
           Tested on Amenia and Reef boards.
    
    Change-Id: I3ba79fa53ca8817149d585fa795a8f427c128dcb
    Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
---
 src/soc/intel/apollolake/include/soc/pm.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index 99f922f..b0e2da2 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -119,6 +119,11 @@
 #define GPE0_STS(x)		(0x20 + (x * 4))
 #define GPE0_EN(x)		(0x30 + (x * 4))
 #define   PME_B0_EN		(1 << 13)
+/*
+ * Enables the setting of the GPIO_TIER1_SCI_STS bit to generate a wake event
+ * and/or an SCI or SMI#.
+ */
+#define GPIO_TIER_1_SCI		(1 << 15)
 
 /* Memory mapped IO registers behind PMC_BASE_ADDRESS */
 #define PRSTS			0x1000