[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Properly disable PCIe root ports

[Kane Chen (kane.chen@intel.com)]

Kane Chen (kane.chen at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15595

-gerrit

commit d24e2097abbde85656a84ef020be803341cdb3a7
Author: Kane Chen <kane.chen at intel.com>
Date:   Mon Jul 11 12:17:13 2016 +0800

    soc/intel/apollolake: Properly disable PCIe root ports
    
    1. The hotplug feature needs to be disabled
       so that pcie root ports will be disabled by fsp
    2. Correct PcieRootPortEn mapping.
    The correct mapping should be like below
    PcieRootPortEn[0] ==>  00:14.0
    PcieRootPortEn[1] ==>  00:14.1
    PcieRootPortEn[2] ==>  00:13.0
    PcieRootPortEn[3] ==>  00:13.1
    PcieRootPortEn[4] ==>  00:13.2
    PcieRootPortEn[5] ==>  00:13.3
    
    BUG=chrome-os-partner:54288
    BRANCH=None
    TEST=Checked pcie root port is disabled properly
    and make sure pcie ports are coalesced.
    Also make sure the device will still be enabled after coalescence
    when pcie on function 0 is disabled devicetree
    
    Change-Id: I39c482a0c068ddc2cc573499480c3fe6a52dd5eb
    Signed-off-by: Kane Chen <kane.chen at intel.com>
---
 src/soc/intel/apollolake/chip.c | 57 ++++++++++++++++++++++++++++++++++++-----
 1 file changed, 51 insertions(+), 6 deletions(-)

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index ae9f09e..79a3f38 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -140,6 +140,42 @@ static void enable_dev(device_t dev)
 	}
 }
 
+/*
+ * If the PCIe root port at function 0 is disabled,
+ * the PCIe root ports might be coalesced after FSP silicon init.
+ * The below function will override the 'enabled' setting in devicetree
+ * by checking if root port is disabled/enabled/coalesced
+ * so that it won't confuse coreboot.
+ */
+static void pcie_override_devicetree_after_silicon_init(void)
+{
+	/* APL only has 6 PCIe root ports */
+	#define num_pcie_rp 6
+	device_t dev;
+
+	/* The below array contains all PCIe rp dev func number */
+	unsigned int pcie_rp_array[num_pcie_rp] = {PCIEA0_DEVFN, PCIEA1_DEVFN,
+		PCIEA2_DEVFN, PCIEA3_DEVFN, PCIEB0_DEVFN, PCIEB1_DEVFN};
+
+	unsigned int vid;
+	int i;
+
+	/*
+	 * Scan all PCIe root ports and make sure it exists or not
+	 * Then override the 'enabled' in devicetree properly
+	 */
+	for (i = 0; i < num_pcie_rp; i++) {
+		dev = dev_find_slot(0, pcie_rp_array[i]);
+		vid = pci_read_config32(dev, PCI_VENDOR_ID);
+
+		/* enable/disable according to device state */
+		if (vid != 0xFFFFFFFF)
+			dev->enabled = 1;
+		else
+			dev->enabled = 0;
+	}
+}
+
 static void soc_init(void *data)
 {
 	struct range_entry range;
@@ -154,6 +190,9 @@ static void soc_init(void *data)
 	range_entry_init(&range, 0x200000, 4ULL*GiB, 0);
 	fsp_silicon_init(&range);
 
+	/* override 'enabled' setting in device tree if needed */
+	pcie_override_devicetree_after_silicon_init();
+
 	/*
 	 * Keep the P2SB device visible so it and the other devices are
 	 * visible in coreboot for driver support and PCI resource allocation.
@@ -186,23 +225,29 @@ static void disable_dev(struct device *dev, struct FSP_S_CONFIG *silconfig) {
 	case SATA_DEVFN:
 		silconfig->EnableSata = 0;
 		break;
-	case PCIEA0_DEVFN:
+	case PCIEB0_DEVFN:
 		silconfig->PcieRootPortEn[0] = 0;
+		silconfig->PcieRpHotPlug[0] = 0;
 		break;
-	case PCIEA1_DEVFN:
+	case PCIEB1_DEVFN:
 		silconfig->PcieRootPortEn[1] = 0;
+		silconfig->PcieRpHotPlug[1] = 0;
 		break;
-	case PCIEA2_DEVFN:
+	case PCIEA0_DEVFN:
 		silconfig->PcieRootPortEn[2] = 0;
+		silconfig->PcieRpHotPlug[2] = 0;
 		break;
-	case PCIEA3_DEVFN:
+	case PCIEA1_DEVFN:
 		silconfig->PcieRootPortEn[3] = 0;
+		silconfig->PcieRpHotPlug[3] = 0;
 		break;
-	case PCIEB0_DEVFN:
+	case PCIEA2_DEVFN:
 		silconfig->PcieRootPortEn[4] = 0;
+		silconfig->PcieRpHotPlug[4] = 0;
 		break;
-	case PCIEB1_DEVFN:
+	case PCIEA3_DEVFN:
 		silconfig->PcieRootPortEn[5] = 0;
+		silconfig->PcieRpHotPlug[5] = 0;
 		break;
 	case XHCI_DEVFN:
 		silconfig->Usb30Mode = 0;