[coreboot-gerrit] New patch to review for coreboot: mainboard/bap/ode_e20XX: Enable UART2/3, 2x PCIe

[Fabian Kunkel (fabi@adv.bruhnspace.com)]

Fabian Kunkel (fabi at adv.bruhnspace.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15621

-gerrit

commit cef3242b84c8a6a7fc46561a9aae7cad45c99c0c
Author: Fabian Kunkel <fabi at adv.bruhnspace.com>
Date:   Tue Jul 12 11:32:37 2016 +0200

    mainboard/bap/ode_e20XX: Enable UART2/3, 2x PCIe
    
    This patch adds support for UART 3/4.
    It also binds PCIe lanes 2-3 together,
    too enable 2x PCIe for the FPGA.
    UART and PCIe functionalities are successfully tested.
    
    Change-Id: I1d8fa16950079a47775f48166486415bd5d24f42
    Signed-off-by: Fabian Kunkel <fabi at adv.bruhnspace.com>
---
 src/mainboard/bap/ode_e20XX/OemCustomize.c | 45 +++++++++++++-----------------
 src/mainboard/bap/ode_e20XX/devicetree.cb  | 11 +++++---
 2 files changed, 27 insertions(+), 29 deletions(-)

diff --git a/src/mainboard/bap/ode_e20XX/OemCustomize.c b/src/mainboard/bap/ode_e20XX/OemCustomize.c
index 7feab3a..1f6a6c8 100644
--- a/src/mainboard/bap/ode_e20XX/OemCustomize.c
+++ b/src/mainboard/bap/ode_e20XX/OemCustomize.c
@@ -25,50 +25,45 @@
 #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
 
 static const PCIe_PORT_DESCRIPTOR PortList [] = {
+	/* Initialize Port descriptor (PCIe port, Lanes 2-3, Dev 2, Func 4) */
 	{
 		0,
-		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),
-		PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5,
-				HotplugBasic,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x01, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2),
-		PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 3),
+		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
+				2, 4,
 				HotplugBasic,
 				PcieGenMaxSupported,
 				PcieGenMaxSupported,
 				AspmDisabled, 0x02, 0)
 	},
-	/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
+	/* Initialize Port descriptor (PCIe port, Lane 1, Dev 2, Func 3) */
 	{
 		0,
-		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1),
-		PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
+		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
+				2, 3,
 				HotplugDisabled,
 				PcieGenMaxSupported,
 				PcieGenMaxSupported,
 				AspmDisabled, 0x03, 0)
 	},
-	/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
+	/* Initialize Port descriptor (PCIe port, Lane 0, Dev 2, Func 2) */
 	{
 		0,
-		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0),
-		PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
+		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
+				2, 2,
 				HotplugDisabled,
 				PcieGenMaxSupported,
 				PcieGenMaxSupported,
 				AspmDisabled, 0x04, 0)
 	},
-	/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
+	/* Initialize Port descriptor (PCIe port, Lanes 4-7, Dev 2, Func 1) */
 	{
 		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
-		PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
+		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db,
+				2, 1,
 				HotplugBasic,
 				PcieGenMaxSupported,
 				PcieGenMaxSupported,
@@ -80,14 +75,14 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = {
 	/* eDP0 to LVDS connector*/
 	{
 		0,
-		PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
-		PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
+		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
 	},
 	/* DP1 to HDMI */
 	{
 		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
-		PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2)
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
+		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux2, Hdp2)
 	},
 };
 
diff --git a/src/mainboard/bap/ode_e20XX/devicetree.cb b/src/mainboard/bap/ode_e20XX/devicetree.cb
index a598a99..ad1e36e 100644
--- a/src/mainboard/bap/ode_e20XX/devicetree.cb
+++ b/src/mainboard/bap/ode_e20XX/devicetree.cb
@@ -31,8 +31,7 @@ chip northbridge/amd/agesa/family16kb/root_complex
 				device pci 2.1 on  end # x4 PCIe Slot
 				device pci 2.2 on  end # PCIe Q7 Realtek GBit LAN
 				device pci 2.3 on  end # PCIe CB Realtek GBit LAN
-				device pci 2.4 on  end # PCIe BAP FPGA
-				device pci 2.5 on  end # PCIe BAP FPGA (unused, for 050T)
+				device pci 2.4 on  end # x2 PCIe BAP FPGA
 			end	#chip northbridge/amd/agesa/family16kb
 
 			chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
@@ -88,9 +87,13 @@ chip northbridge/amd/agesa/family16kb/root_complex
 							io 0x60 = 0x2f8
 							irq 0x70 = 3
 						end
-						device pnp 4e.12 off			# COM3
+						device pnp 4e.12 on			# COM3
+							io 0x60 = 0x3e8
+							irq 0x70 = 4
 						end
-						device pnp 4e.13 off			# COM4
+						device pnp 4e.13 on			# COM4
+							io 0x60 = 0x2e8
+							irq 0x70 = 3
 						end
 						device pnp 4e.14 off			# COM5
 						end