[coreboot-gerrit] Patch set updated for coreboot: intel/amenia: Enable DPTF
Shaunak Saha (shaunak.saha@intel.com)
gerrit at coreboot.org
Tue Jul 12 11:10:45 CEST 2016
Shaunak Saha (shaunak.saha at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15094
-gerrit
commit d2e30577a70336c025d8e032e086e92c36cfbd9e
Author: Shaunak Saha <shaunak.saha at intel.com>
Date: Tue Jun 7 00:29:48 2016 -0700
intel/amenia: Enable DPTF
This patch enables DPTF support for Intel Amenia
platform, adds the ASL settings specific to Amenia
boards.
BUG = 53096
TEST = Verify that the thermal zones are enumerated
under /sys/class/thermal. Navigate to
/sys/class/thermal, and verify that a thermal
zone of type TCPU exists there.
Change-Id: I400e2312a20870058f3a386004fad748d3ee4460
Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
---
src/mainboard/intel/amenia/acpi/dptf.asl | 131 +++++++++++++++++++++++++++++++
src/mainboard/intel/amenia/devicetree.cb | 3 +
src/mainboard/intel/amenia/dsdt.asl | 5 ++
3 files changed, 139 insertions(+)
diff --git a/src/mainboard/intel/amenia/acpi/dptf.asl b/src/mainboard/intel/amenia/acpi/dptf.asl
new file mode 100644
index 0000000..d4899d4
--- /dev/null
+++ b/src/mainboard/intel/amenia/acpi/dptf.asl
@@ -0,0 +1,131 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE 80
+#define DPTF_CPU_CRITICAL 90
+#define DPTF_CPU_ACTIVE_AC0 90
+#define DPTF_CPU_ACTIVE_AC1 80
+#define DPTF_CPU_ACTIVE_AC2 70
+#define DPTF_CPU_ACTIVE_AC3 60
+#define DPTF_CPU_ACTIVE_AC4 50
+
+#define DPTF_TSR0_SENSOR_ID 0
+#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal"
+#define DPTF_TSR0_PASSIVE 48
+#define DPTF_TSR0_CRITICAL 70
+
+#define DPTF_TSR1_SENSOR_ID 1
+#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top"
+#define DPTF_TSR1_PASSIVE 60
+#define DPTF_TSR1_CRITICAL 70
+
+#define DPTF_TSR2_SENSOR_ID 2
+#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE 55
+#define DPTF_TSR2_CRITICAL 70
+
+#define DPTF_ENABLE_CHARGER
+#define DPTF_ENABLE_FAN_CONTROL
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+ Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */
+ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
+ Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
+})
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+/* DFPS: Fan Performance States */
+Name (DFPS, Package () {
+ 0, // Revision
+ /*
+ * TODO: Need to update this table after characterization.
+ * These are initial reference values.
+ */
+ /* Control, Trip Point, Speed, NoiseLevel, Power */
+ Package () {100, 0xFFFFFFFF, 4986, 220, 2200},
+ Package () {90, 0xFFFFFFFF, 4804, 180, 1800},
+ Package () {80, 0xFFFFFFFF, 4512, 145, 1450},
+ Package () {70, 0xFFFFFFFF, 4204, 115, 1150},
+ Package () {60, 0xFFFFFFFF, 3838, 90, 900},
+ Package () {50, 0xFFFFFFFF, 3402, 65, 650},
+ Package () {40, 0xFFFFFFFF, 2904, 45, 450},
+ Package () {30, 0xFFFFFFFF, 2337, 30, 300},
+ Package () {20, 0xFFFFFFFF, 1608, 15, 150},
+ Package () {10, 0xFFFFFFFF, 800, 10, 100},
+ Package () {0, 0xFFFFFFFF, 0, 0, 50}
+})
+
+Name (DART, Package () {
+ /* Fan effect on CPU */
+ 0, // Revision
+ Package () {
+ /*
+ * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,
+ * AC7, AC8, AC9
+ */
+ \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 100, 90, 80, 70, 60, 0, 0,
+ 0, 0, 0
+ }
+})
+#endif
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 0 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+ /* Charger Effect on Temp Sensor 1 */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
+#endif
+
+ /* CPU Effect on Temp Sensor 1 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 2 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, /* Revision */
+ Package () { /* Power Limit 1 */
+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
+ 1600, /* PowerLimitMinimum */
+ 15000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 200 /* StepSize */
+ },
+ Package () { /* Power Limit 2 */
+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
+ 8000, /* PowerLimitMinimum */
+ 8000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 1000 /* StepSize */
+ }
+})
+
+/* Include soc specific DPTF changes */
+#include <soc/intel/apollolake/acpi/dptf.asl>
+/* Include intel common dptf */
+#include <soc/intel/common/acpi/dptf/dptf.asl>
diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb
index 7045f59..af2a1f6 100644
--- a/src/mainboard/intel/amenia/devicetree.cb
+++ b/src/mainboard/intel/amenia/devicetree.cb
@@ -18,6 +18,9 @@ chip soc/intel/apollolake
# LPSS S0ix Enable
register "lpss_s0ix_enable" = "1"
+ # Enable DPTF
+ register "dptf_enable" = "1"
+
device domain 0 on
device pci 00.0 on end # - Host Bridge
device pci 00.1 on end # - DPTF
diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl
index 46404ed..c106473 100644
--- a/src/mainboard/intel/amenia/dsdt.asl
+++ b/src/mainboard/intel/amenia/dsdt.asl
@@ -45,4 +45,9 @@ DefinitionBlock(
#include <soc/intel/apollolake/acpi/sleepstates.asl>
#include "acpi/superio.asl"
+
+ Scope (\_SB) {
+ /* Dynamic Platform Thermal Framework */
+ #include "acpi/dptf.asl"
+ }
}
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