[coreboot-gerrit] Patch set updated for coreboot: Intel/x4x correct DDR2 latency
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Tue Jul 12 09:51:17 CEST 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15541
-gerrit
commit 86b9d7bdd1ff5eab92d51374350b575aebd6c616
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Sun Jul 3 17:08:31 2016 +0200
Intel/x4x correct DDR2 latency
Correct latency decode for DDR2.
DDR2 may support latency 2, 3,..,7. (bit#2,... bit#7)
Common value (or mask) should be 0xfc.
Change-Id: Ic3e910021a0ff53f43dec21ebe8c98f1d90ba639
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/northbridge/intel/x4x/raminit.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 4f5575c..e342e4b 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -111,10 +111,7 @@ static void sdram_read_spds(struct sysinfo *s)
s->dimms[i].chip_capacity = s->dimms[i].banks;
s->dimms[i].rows = s->dimms[i].spd_data[3];// - 12;
s->dimms[i].cols = s->dimms[i].spd_data[4];// - 9;
- s->dimms[i].cas_latencies = 0x78;
- s->dimms[i].cas_latencies &= s->dimms[i].spd_data[18];
- if (s->dimms[i].cas_latencies == 0)
- s->dimms[i].cas_latencies = 7;
+ s->dimms[i].cas_latencies = (s->dimms[i].spd_data[18] & 0xfc);
s->dimms[i].tAAmin = s->dimms[i].spd_data[26];
s->dimms[i].tCKmin = s->dimms[i].spd_data[25];
s->dimms[i].width = (s->dimms[i].spd_data[13] >> 3) - 1;
@@ -332,7 +329,7 @@ static void sdram_detect_ram_speed(struct sysinfo *s)
}
// Detect a common CAS latency
- commoncas = 0xff;
+ commoncas = 0xfc;
FOR_EACH_POPULATED_DIMM(s->dimms, i) {
commoncas &= s->dimms[i].spd_data[18];
}
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