[coreboot-gerrit] Patch set updated for coreboot: arch: Add ARMv7-R configuration
hakim giydan (hgiydan@marvell.com)
gerrit at coreboot.org
Mon Jul 11 17:04:38 CEST 2016
hakim giydan (hgiydan at marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15335
-gerrit
commit 34ee4c86f6f569ed23bc49e64c7d2866a58676d8
Author: Hakim Giydan <hgiydan at marvell.com>
Date: Fri Jul 8 14:23:31 2016 -0700
arch: Add ARMv7-R configuration
This change adds armv7-r configuration for romstage and verstage,
and any other files needed to initialize an armv7-r processor.
ARMv7-R is an ARM processor based on the Cortex-R series.
Currently, there is already support for the Cortex-M series,
so the same files had been renamed and reused for Cortex-R series
as well.
Change-Id: If94415d07fd6bd96c43d087374f609a2211f1885
Signed-off-by: Hakim Giydan <hgiydan at marvell.com>
---
src/arch/arm/armv7/Kconfig | 8 ++++
src/arch/arm/armv7/Makefile.inc | 27 ++++++++++++-
src/arch/arm/armv7/cache_m.c | 79 ---------------------------------------
src/arch/arm/armv7/cache_mr.c | 79 +++++++++++++++++++++++++++++++++++++++
src/arch/arm/armv7/cpu_r.S | 65 ++++++++++++++++++++++++++++++++
src/arch/arm/armv7/exception_m.c | 36 ------------------
src/arch/arm/armv7/exception_mr.c | 36 ++++++++++++++++++
util/xcompile/xcompile | 2 +-
8 files changed, 214 insertions(+), 118 deletions(-)
diff --git a/src/arch/arm/armv7/Kconfig b/src/arch/arm/armv7/Kconfig
index 0ab3542..4fe3fd7 100644
--- a/src/arch/arm/armv7/Kconfig
+++ b/src/arch/arm/armv7/Kconfig
@@ -19,3 +19,11 @@ config ARCH_BOOTBLOCK_ARMV7_M
config ARCH_VERSTAGE_ARMV7_M
def_bool n
select ARCH_VERSTAGE_ARM
+
+config ARCH_VERSTAGE_ARMV7_R
+ def_bool n
+ select ARCH_VERSTAGE_ARM
+
+config ARCH_ROMSTAGE_ARMV7_R
+ def_bool n
+ select ARCH_ROMSTAGE_ARM
diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc
index 2e9c49c..63617f1 100644
--- a/src/arch/arm/armv7/Makefile.inc
+++ b/src/arch/arm/armv7/Makefile.inc
@@ -46,8 +46,8 @@ bootblock-S-ccopts += $(armv7_asm_flags)
ifneq ($(CONFIG_BOOTBLOCK_CUSTOM),y)
bootblock-y += bootblock_m.S
endif
-bootblock-y += exception_m.c
-bootblock-y += cache_m.c
+bootblock-y += exception_mr.c
+bootblock-y += cache_mr.c
endif # CONFIG_ARCH_BOOTBLOCK_ARMV7
@@ -73,6 +73,17 @@ libverstage-S-ccopts += $(armv7_asm_flags)
verstage-generic-ccopts += $(armv7-m_flags)
verstage-S-ccopts += $(armv7_asm_flags)
+else ifeq ($(CONFIG_ARCH_VERSTAGE_ARMV7_R),y)
+libverstage-generic-ccopts += $(armv7-r_flags)
+libverstage-S-ccopts += $(armv7-r_asm_flags)
+verstage-generic-ccopts += $(armv7-r_flags)
+verstage-S-ccopts += $(armv7-r_asm_flags)
+
+verstage-y += cache_mr.c
+verstage-y += cpu_r.S
+verstage-y += exception_mr.c
+verstage-y += mmu.c
+
endif # CONFIG_ARCH_VERSTAGE_ARMV7_M
################################################################################
@@ -91,6 +102,18 @@ romstage-S-ccopts += $(armv7_asm_flags)
rmodules_arm-generic-ccopts += $(armv7-a_flags)
rmodules_arm-S-ccopts += $(armv7_asm_flags)
+else ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV7_R),y)
+romstage-y += cache_mr.c
+romstage-y += cpu_r.S
+romstage-y += exception_mr.c
+romstage-y += mmu.c
+
+romstage-generic-ccopts += $(armv7-r_flags)
+romstage-S-ccopts += $(armv7-r_asm_flags)
+
+rmodules_arm-generic-ccopts += $(armv7-r_flags)
+rmodules_arm-S-ccopts += $(armv7-r_asm_flags)
+
endif # CONFIG_ARCH_ROMSTAGE_ARMV7
###############################################################################
diff --git a/src/arch/arm/armv7/cache_m.c b/src/arch/arm/armv7/cache_m.c
deleted file mode 100644
index ec8a970..0000000
--- a/src/arch/arm/armv7/cache_m.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * cache.c: Cache maintenance routines for ARMv7-M
- */
-
-#include <stdint.h>
-
-#include <arch/cache.h>
-
-void tlb_invalidate_all(void)
-{
-}
-
-void dcache_clean_all(void)
-{
-}
-
-void dcache_clean_invalidate_all(void)
-{
-}
-
-void dcache_invalidate_all(void)
-{
-}
-
-unsigned int dcache_line_bytes(void)
-{
- return 0;
-}
-
-void dcache_clean_by_mva(void const *addr, size_t len)
-{
-}
-
-void dcache_clean_invalidate_by_mva(void const *addr, size_t len)
-{
-}
-
-void dcache_invalidate_by_mva(void const *addr, size_t len)
-{
-}
-
-void dcache_mmu_disable(void)
-{
-}
-
-void dcache_mmu_enable(void)
-{
-}
-
-void cache_sync_instructions(void)
-{
-}
diff --git a/src/arch/arm/armv7/cache_mr.c b/src/arch/arm/armv7/cache_mr.c
new file mode 100644
index 0000000..ec8a970
--- /dev/null
+++ b/src/arch/arm/armv7/cache_mr.c
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * cache.c: Cache maintenance routines for ARMv7-M
+ */
+
+#include <stdint.h>
+
+#include <arch/cache.h>
+
+void tlb_invalidate_all(void)
+{
+}
+
+void dcache_clean_all(void)
+{
+}
+
+void dcache_clean_invalidate_all(void)
+{
+}
+
+void dcache_invalidate_all(void)
+{
+}
+
+unsigned int dcache_line_bytes(void)
+{
+ return 0;
+}
+
+void dcache_clean_by_mva(void const *addr, size_t len)
+{
+}
+
+void dcache_clean_invalidate_by_mva(void const *addr, size_t len)
+{
+}
+
+void dcache_invalidate_by_mva(void const *addr, size_t len)
+{
+}
+
+void dcache_mmu_disable(void)
+{
+}
+
+void dcache_mmu_enable(void)
+{
+}
+
+void cache_sync_instructions(void)
+{
+}
diff --git a/src/arch/arm/armv7/cpu_r.S b/src/arch/arm/armv7/cpu_r.S
new file mode 100644
index 0000000..6d5820e
--- /dev/null
+++ b/src/arch/arm/armv7/cpu_r.S
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2010 Per Odlund <per.odlund at armagedon.se>
+ * Copyright (c) 2014 Google Inc.
+ * Copyright (c) 2016 Marvell Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <arch/asm.h>
+
+/*
+ * Bring an ARM processor we just gained control of (e.g. from IROM) into a
+ * known state regarding caches/SCTLR. Completely cleans and invalidates
+ * icache/dcache, and dcache (if active), and enables unaligned
+ * accesses, icache and branch prediction (if inactive). Clobbers r4 and r5.
+ *
+ * THIS FUNCTION MUST PRESERVE THE VALUE OF r10
+ */
+ENTRY(arm_init_caches)
+ /* r4: SCTLR, return address: r5 (stay valid for the whole function) */
+ mov r5, lr
+ mrc p15, 0, r4, c1, c0, 0
+
+ /* Activate ICache (12) and Branch Prediction (11) already for speed */
+ orr r4, # (1 << 11) | (1 << 12)
+ mcr p15, 0, r4, c1, c0, 0
+
+ /* Flush and invalidate dcache in ascending order */
+ bl dcache_invalidate_all
+
+ /* Deactivate Alignment Check (1) and DCache (2) */
+ and r4, # ~(1 << 1) & ~(1 << 2)
+ mcr p15, 0, r4, c1, c0, 0
+
+ /* Invalidate icache for good measure */
+ mcr p15, 0, r0, c7, c5, 0
+
+ dsb
+ isb
+
+ bx r5
+ENDPROC(arm_init_caches)
diff --git a/src/arch/arm/armv7/exception_m.c b/src/arch/arm/armv7/exception_m.c
deleted file mode 100644
index d76cc6a..0000000
--- a/src/arch/arm/armv7/exception_m.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is part of the libpayload project.
- *
- * Copyright 2013 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <arch/exception.h>
-#include <console/console.h>
-
-void exception_init(void)
-{
- printk(BIOS_DEBUG, "Exception handlers not installed.\n");
-}
diff --git a/src/arch/arm/armv7/exception_mr.c b/src/arch/arm/armv7/exception_mr.c
new file mode 100644
index 0000000..d76cc6a
--- /dev/null
+++ b/src/arch/arm/armv7/exception_mr.c
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <arch/exception.h>
+#include <console/console.h>
+
+void exception_init(void)
+{
+ printk(BIOS_DEBUG, "Exception handlers not installed.\n");
+}
diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index 13a0e8f..1a9c38c 100755
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -316,7 +316,7 @@ arch_config_arm() {
TBFDARCHS="littlearm"
TCLIST="armv7-a armv7a arm"
TWIDTH="32"
- TSUPP="arm armv4 armv7 armv7_m"
+ TSUPP="arm armv4 armv7 armv7_m armv7_r"
TABI="eabi"
}
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