[coreboot-gerrit] Patch set updated for coreboot: superio/fintek/f81866d: Add support for UART 3/4
Fabian Kunkel (fabi@adv.bruhnspace.com)
gerrit at coreboot.org
Mon Jul 11 15:39:21 CEST 2016
Fabian Kunkel (fabi at adv.bruhnspace.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15564
-gerrit
commit ee5e1d359f61bb2cb2442d8c9e7e86cc651f4b26
Author: Fabian Kunkel <fabi at adv.bruhnspace.com>
Date: Thu Jul 7 15:15:18 2016 +0200
superio/fintek/f81866d: Add support for UART 3/4
Pins for UART 3/4 are by default GPIO pins.
This patch sets the pins in UART mode.
Since UART 1/3 and 2/4 share the same interrupt line,
the patch needs to enable also shared interrupts.
Datasheet: Name: F81866D/A-I, Release Date: Jan 2012, Version: V0.12P
Link: http://www.alldatasheet.com/datasheet-pdf/pdf/459085/FINTEK/F81866AD-I.html
Change-Id: Ief5d70c8b25a2fb6cd787c45a52410e20b0eaf2e
Signed-off-by: Fabian Kunkel <fabi at adv.bruhnspace.com>
---
src/superio/fintek/f81866d/Makefile.inc | 2 +-
src/superio/fintek/f81866d/f81866d_uart.c | 92 ++++++++++++++++++++++++++++
src/superio/fintek/f81866d/fintek_internal.h | 1 +
src/superio/fintek/f81866d/superio.c | 8 +++
4 files changed, 102 insertions(+), 1 deletion(-)
diff --git a/src/superio/fintek/f81866d/Makefile.inc b/src/superio/fintek/f81866d/Makefile.inc
index 8654659..b3fd34f 100644
--- a/src/superio/fintek/f81866d/Makefile.inc
+++ b/src/superio/fintek/f81866d/Makefile.inc
@@ -16,5 +16,5 @@
## GNU General Public License for more details.
##
-ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += f81866d_hwm.c
+ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += f81866d_hwm.c f81866d_uart.c
ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += superio.c
diff --git a/src/superio/fintek/f81866d/f81866d_uart.c b/src/superio/fintek/f81866d/f81866d_uart.c
new file mode 100644
index 0000000..49f9597
--- /dev/null
+++ b/src/superio/fintek/f81866d/f81866d_uart.c
@@ -0,0 +1,92 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects
+ * (Written by Fabian Kunkel <fabi at adv.bruhnspace.com> for BAP)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include "fintek_internal.h"
+#include "f81866d.h"
+
+#define LDN_REG 0x07
+#define MULTI_FUNC_SEL3_REG 0x29
+#define IRQ_SHARE_REGISTER 0xF0
+#define FIFO_SEL_MODE 0xF6
+
+/*
+ * f81866d_uart_init enables all necessary registers for UART 3/4
+ * Fintek needs to know if pins are used as GPIO or UART pins
+ * Share interrupt usage needs to be enabled
+ */
+void f81866d_uart_init(struct device *dev)
+{
+ struct resource *res = find_resource(dev, PNP_IDX_IO0);
+ u8 tmp;
+
+ if (!res) {
+ printk(BIOS_WARNING, "%s: No UART resource found.\n", __func__);
+ return;
+ }
+
+ pnp_enter_conf_mode(dev);
+
+ if (dev->path.pnp.device == F81866D_SP3) {
+ // Set UART 3 function (Bit 4/5), otherwise pin 36-46 are GPIO
+ tmp = pnp_read_config(dev, MULTI_FUNC_SEL3_REG);
+ pnp_write_config(dev, MULTI_FUNC_SEL3_REG, tmp | 0x30);
+
+ // Select UART 1 in LDN register
+ pnp_write_config(dev, LDN_REG, F81866D_SP1 & 0xff);
+ // Enable share interrupt (Bit 0)
+ pnp_write_config(dev, IRQ_SHARE_REGISTER, 0x01);
+ // Set IRQ trigger mode from active low to high (Bit 3)
+ tmp = pnp_read_config(dev, FIFO_SEL_MODE);
+ pnp_write_config(dev, FIFO_SEL_MODE, tmp | 0x8);
+
+ // Select UART 3 in LDN register
+ pnp_write_config(dev, LDN_REG, F81866D_SP3 & 0xff);
+ // Enable share interrupt (Bit 0)
+ pnp_write_config(dev, IRQ_SHARE_REGISTER, 0x01);
+ // Set IRQ trigger mode from active low to high (Bit 3)
+ tmp = pnp_read_config(dev, FIFO_SEL_MODE);
+ pnp_write_config(dev, FIFO_SEL_MODE, tmp | 0x8);
+ }
+
+ if (dev->path.pnp.device == F81866D_SP4) {
+ // Set UART 4 function (Bit 6/7), otherwise pin 44-51 are GPIO
+ tmp = pnp_read_config(dev, MULTI_FUNC_SEL3_REG);
+ pnp_write_config(dev, MULTI_FUNC_SEL3_REG, tmp | 0xC0);
+
+ // Select UART 2 in LDN register
+ pnp_write_config(dev, LDN_REG, F81866D_SP2 & 0xff);
+ // Enable share interrupt (Bit 0)
+ pnp_write_config(dev, IRQ_SHARE_REGISTER, 0x01);
+ // Set IRQ trigger mode from active low to high (Bit 3)
+ tmp = pnp_read_config(dev, FIFO_SEL_MODE);
+ pnp_write_config(dev, FIFO_SEL_MODE, tmp | 0x8);
+
+ // Select UART 4 in LDN register
+ pnp_write_config(dev, LDN_REG, F81866D_SP4 & 0xff);
+ // Enable share interrupt (Bit 0)
+ pnp_write_config(dev, IRQ_SHARE_REGISTER, 0x01);
+ // Set IRQ trigger mode from active low to high (Bit 3)
+ tmp = pnp_read_config(dev, FIFO_SEL_MODE);
+ pnp_write_config(dev, FIFO_SEL_MODE, tmp | 0x8);
+ }
+
+ pnp_exit_conf_mode(dev);
+}
diff --git a/src/superio/fintek/f81866d/fintek_internal.h b/src/superio/fintek/f81866d/fintek_internal.h
index 0405e3e..977a47d 100644
--- a/src/superio/fintek/f81866d/fintek_internal.h
+++ b/src/superio/fintek/f81866d/fintek_internal.h
@@ -23,5 +23,6 @@
#include <device/pnp.h>
void f81866d_hwm_init(struct device *dev);
+void f81866d_uart_init(struct device *dev);
#endif /* SUPERIO_FINTEK_F81866D_INTERNAL_H */
diff --git a/src/superio/fintek/f81866d/superio.c b/src/superio/fintek/f81866d/superio.c
index a616290..c997ce3 100644
--- a/src/superio/fintek/f81866d/superio.c
+++ b/src/superio/fintek/f81866d/superio.c
@@ -40,6 +40,14 @@ static void f81866d_init(struct device *dev)
// Fixing temp sensor read out and init Fan control
f81866d_hwm_init(dev);
break;
+ case F81866D_SP3:
+ // Enable Uart3 and IRQ share register
+ f81866d_uart_init(dev);
+ break;
+ case F81866D_SP4:
+ // Enable Uart4 and IRQ share register
+ f81866d_uart_init(dev);
+ break;
}
}
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