[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: fixed pcie root ports are not disabled properly

[Kane Chen (kane.chen@intel.com)]

Kane Chen (kane.chen at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15595

-gerrit

commit a7da5c4178e316454ff4619b7d9cbb8a9c53d9f3
Author: Kane Chen <kane.chen at intel.com>
Date:   Mon Jul 11 12:17:13 2016 +0800

    soc/intel/apollolake: fixed pcie root ports are not disabled properly
    
    1. The hotplug feature need to be disabled so that pcie root ports will be disabled by fsp
    2. Correct PcieRootPortEn mapping.
    The correct mapping should be like below
    PcieRootPortEn[0] ==>  00:14.0
    PcieRootPortEn[1] ==>  00:14.1
    PcieRootPortEn[2] ==>  00:13.0
    PcieRootPortEn[3] ==>  00:13.1
    PcieRootPortEn[4] ==>  00:13.2
    PcieRootPortEn[5] ==>  00:13.3
    
    BUG=chrome-os-partner:54288
    BRANCH=None
    TEST=checked pcie root ports are disabled according with devicetree.cb
    
    Change-Id: I39c482a0c068ddc2cc573499480c3fe6a52dd5eb
    Signed-off-by: Kane Chen <kane.chen at intel.com>
---
 src/soc/intel/apollolake/chip.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index ae9f09e..f5936b2 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -186,23 +186,29 @@ static void disable_dev(struct device *dev, struct FSP_S_CONFIG *silconfig) {
 	case SATA_DEVFN:
 		silconfig->EnableSata = 0;
 		break;
-	case PCIEA0_DEVFN:
+	case PCIEB0_DEVFN:
 		silconfig->PcieRootPortEn[0] = 0;
+		silconfig->PcieRpHotPlug[0] = 0;
 		break;
-	case PCIEA1_DEVFN:
+	case PCIEB1_DEVFN:
 		silconfig->PcieRootPortEn[1] = 0;
+		silconfig->PcieRpHotPlug[1] = 0;
 		break;
-	case PCIEA2_DEVFN:
+	case PCIEA0_DEVFN:
 		silconfig->PcieRootPortEn[2] = 0;
+		silconfig->PcieRpHotPlug[2] = 0;
 		break;
-	case PCIEA3_DEVFN:
+	case PCIEA1_DEVFN:
 		silconfig->PcieRootPortEn[3] = 0;
+		silconfig->PcieRpHotPlug[3] = 0;
 		break;
-	case PCIEB0_DEVFN:
+	case PCIEA2_DEVFN:
 		silconfig->PcieRootPortEn[4] = 0;
+		silconfig->PcieRpHotPlug[4] = 0;
 		break;
-	case PCIEB1_DEVFN:
+	case PCIEA3_DEVFN:
 		silconfig->PcieRootPortEn[5] = 0;
+		silconfig->PcieRpHotPlug[5] = 0;
 		break;
 	case XHCI_DEVFN:
 		silconfig->Usb30Mode = 0;