[coreboot-gerrit] Patch set updated for coreboot: Add support for F2950 single-board computer
Andrey Korolyov (andrey@xdel.ru)
gerrit at coreboot.org
Sun Jul 10 20:11:20 CEST 2016
Andrey Korolyov (andrey at xdel.ru) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15565
-gerrit
commit 55a65d9dcc7f8fe136a78f92a9705747579d41b5
Author: Andrey Korolyov <andrey at xdel.ru>
Date: Fri Jul 1 20:06:37 2016 +0300
Add support for F2950 single-board computer
This platform, also known as TONK 1201/TONK 1202, was originally
produced as a Centerm F2950. Common configuration does include
a 600 MHz GeodeLX CPU underclocked to 500 or 400 MHz, 128 or 512 MiB
of RAM in the single SODIMM slot and 128 or 512 MB IDE DOM. The board
does have three USB 2.0 ports (none of them possessing debug
capabilities), PS/2, VGA, Geode audio in/out and the serial port.
EEPROM needs to be soldered out and flashed externally at the time
of this message because flashrom would neither be able to dump BIOS
correctly while running vendor BIOS nor write flash contents.
At this moment GeodeVGA does not work out-of-box after initialization
by SeaBIOS, thereby preventing trivial selection of the bootable media,
though it is possible to select a necessary boot device using SeaBIOS
with compiled-in serial output and non-zero debug level and a regular
keyboard. Linux`s lxfb driver works fine and the board could be used
for its common purposes. Except this, all peripheral components (USB,
serial, IDE, PS/2, audio and ethernet) are working well.
Change-Id: I93f13ecb53bd05abc0e07e0bd7ba40e646dcb4c4
---
src/mainboard/amd/f2950/Kconfig | 27 ++++++++++++
src/mainboard/amd/f2950/Kconfig.name | 2 +
src/mainboard/amd/f2950/board_info.txt | 6 +++
src/mainboard/amd/f2950/cmos.layout | 36 +++++++++++++++
src/mainboard/amd/f2950/devicetree.cb | 67 ++++++++++++++++++++++++++++
src/mainboard/amd/f2950/irq_tables.c | 64 +++++++++++++++++++++++++++
src/mainboard/amd/f2950/romstage.c | 80 ++++++++++++++++++++++++++++++++++
7 files changed, 282 insertions(+)
diff --git a/src/mainboard/amd/f2950/Kconfig b/src/mainboard/amd/f2950/Kconfig
new file mode 100644
index 0000000..5bfe120
--- /dev/null
+++ b/src/mainboard/amd/f2950/Kconfig
@@ -0,0 +1,27 @@
+if BOARD_AMD_F2950
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_AMD_GEODE_LX
+ select NORTHBRIDGE_AMD_LX
+ select SOUTHBRIDGE_AMD_CS5536
+ select SUPERIO_WINBOND_W83627HF
+ select HAVE_PIRQ_TABLE
+ select PIRQ_ROUTE
+ select UDELAY_TSC
+ select BOARD_ROMSIZE_KB_512
+ select POWER_BUTTON_FORCE_ENABLE
+
+config MAINBOARD_DIR
+ string
+ default amd/f2950
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "F2950"
+
+config IRQ_SLOT_COUNT
+ int
+ default 3
+
+endif # BOARD_AMD_F2950
diff --git a/src/mainboard/amd/f2950/Kconfig.name b/src/mainboard/amd/f2950/Kconfig.name
new file mode 100644
index 0000000..8f6073a
--- /dev/null
+++ b/src/mainboard/amd/f2950/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_AMD_F2950
+ bool "F2950"
diff --git a/src/mainboard/amd/f2950/board_info.txt b/src/mainboard/amd/f2950/board_info.txt
new file mode 100644
index 0000000..e957623
--- /dev/null
+++ b/src/mainboard/amd/f2950/board_info.txt
@@ -0,0 +1,6 @@
+Board name: F2950
+Category: mini
+ROM package: PLCC
+ROM protocol: FWH
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/amd/f2950/cmos.layout b/src/mainboard/amd/f2950/cmos.layout
new file mode 100644
index 0000000..6de5ab6
--- /dev/null
+++ b/src/mainboard/amd/f2950/cmos.layout
@@ -0,0 +1,36 @@
+entries
+
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+456 1 e 1 ECC_memory
+1008 16 h 0 check_sum
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+
+checksums
+
+checksum 392 1007 1008
diff --git a/src/mainboard/amd/f2950/devicetree.cb b/src/mainboard/amd/f2950/devicetree.cb
new file mode 100644
index 0000000..4e563d2
--- /dev/null
+++ b/src/mainboard/amd/f2950/devicetree.cb
@@ -0,0 +1,67 @@
+chip northbridge/amd/lx
+ device domain 0 on
+ device pci 1.0 on end # Northbridge
+ device pci 1.1 on end # Graphics
+ device pci 1.2 on end # Integrated cryptoaccelerator
+ chip southbridge/amd/cs5536
+ # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK
+ # SIRQ Mode = Active(Quiet) mode. Save power....
+ # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
+ register "lpc_serirq_enable" = "0x0000105a"
+ register "lpc_serirq_polarity" = "0x0000EFA5"
+ register "lpc_serirq_mode" = "1"
+ register "enable_gpio_int_route" = "0x0D0C0700"
+ register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+ register "enable_USBP4_device" = "1" # 0: host, 1:device
+ register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+ register "com1_enable" = "0"
+ register "com1_address" = "0x3F8"
+ register "com1_irq" = "4"
+ register "com2_enable" = "0"
+ register "com2_address" = "0x2F8"
+ register "com2_irq" = "3"
+ register "unwanted_vpci[0]" = "0" # End of list has a zero
+ device pci d.0 on end # Ethernet
+ device pci f.0 on # ISA Bridge
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off end # Com2
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GAME_MIDI_GIPO1
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b off end # HW Monitor
+ end
+ end
+ device pci f.2 on end # IDE Controller
+ device pci f.3 on end # Audio
+ device pci f.4 on end # OHCI
+ device pci f.5 on end # EHCI
+ end
+ end
+ # APIC cluster is late CPU init.
+ device cpu_cluster 0 on
+ chip cpu/amd/geode_lx
+ device lapic 0 on end
+ end
+ end
+end
diff --git a/src/mainboard/amd/f2950/irq_tables.c b/src/mainboard/amd/f2950/irq_tables.c
new file mode 100644
index 0000000..b438f02
--- /dev/null
+++ b/src/mainboard/amd/f2950/irq_tables.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/pirq_routing.h>
+#include "southbridge/amd/cs5536/cs5536.h"
+
+/* Platform IRQs */
+#define PIRQA 11
+#define PIRQB 5
+#define PIRQC 10
+#define PIRQD 10
+
+/* Map */
+#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
+#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
+#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
+#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
+
+/* Link */
+#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
+#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
+#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
+#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
+
+static const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
+ (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */
+ 0x00, /* IRQs devoted exclusively to PCI usage */
+ 0x100B, /* Vendor */
+ 0x002B, /* Device */
+ 0, /* Miniport data */
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
+ 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+ {
+ /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */
+ {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */
+ {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+}
diff --git a/src/mainboard/amd/f2950/romstage.c b/src/mainboard/amd/f2950/romstage.c
new file mode 100644
index 0000000..318149d
--- /dev/null
+++ b/src/mainboard/amd/f2950/romstage.c
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <console/console.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/car.h>
+#include <cpu/amd/lxdef.h>
+#include <southbridge/amd/cs5536/cs5536.h>
+#include <spd.h>
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
+#include <northbridge/amd/lx/raminit.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
+int spd_read_byte(unsigned int device, unsigned int address)
+{
+ if (device != DIMM0)
+ return 0xFF;
+
+ return smbus_read_byte(device, address);
+}
+
+#include "northbridge/amd/lx/pll_reset.c"
+#include "lib/generic_sdram.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
+
+void main(unsigned long bist)
+{
+
+ static const struct mem_controller memctrl[] = {
+ {.channel0 = {DIMM0, DIMM1}}
+ };
+
+ SystemPreInit();
+ msr_init();
+
+ cs5536_early_setup();
+
+ /* Note: must do this AFTER the early_setup! It is counting on some
+ * early MSR setup for CS5536.
+ */
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ pll_reset();
+
+ cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
+
+ sdram_initialize(1, memctrl);
+
+ /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
+ return;
+}
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