[coreboot-gerrit] Patch set updated for coreboot: AMD k8 fam10: Separate romstage ramstack (WIP)

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15473

-gerrit

commit ebbb5fe7b3184e790a5f4a60770ea740882fcee6
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Mon Jun 27 19:45:19 2016 +0300

    AMD k8 fam10: Separate romstage ramstack (WIP)
    
    Romstage ram stack was placed below RAMTOP. This is a vulnerable
    location as a large ramstage could overwrite it. Location also
    prevents optimizing S3 resume path since all low memory between
    RAMBASE..RAMTOP has to be backed to CBMEM.
    
    When possible, place ram stack high.
    
    Change-Id: I4106e91ed3256aca5d0d115d4aa7e46b75b27eec
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/cpu/amd/car/post_cache_as_ram.c | 39 +++++++++++--------------------------
 1 file changed, 11 insertions(+), 28 deletions(-)

diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index bf27212..4991b24 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -23,6 +23,7 @@
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/car.h>
 #include <arch/acpi.h>
+#include <program_loading.h>
 #include <romstage_handoff.h>
 #include "cbmem.h"
 #include "cpu/amd/car/disable_cache_as_ram.c"
@@ -37,12 +38,6 @@
 #define print_car_debug(format, arg...)
 #endif
 
-static size_t backup_size(void)
-{
-	size_t car_size = car_data_size();
-	return ALIGN(car_size + 1024, 1024);
-}
-
 static void memcpy_(void *d, const void *s, size_t len)
 {
 	print_car_debug(" Copy [%08x-%08x] to [%08x - %08x] ...",
@@ -63,35 +58,18 @@ static int memcmp_(void *d, const void *s, size_t len)
 	return memcmp(d, s, len);
 }
 
-static void prepare_romstage_ramstack(int s3resume)
-{
-	size_t backup_top = backup_size();
-	print_car_debug("Prepare CAR migration and stack regions...");
-
-	if (s3resume) {
-		void *resume_backup_memory = acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
-		if (resume_backup_memory)
-			memcpy_(resume_backup_memory + HIGH_MEMORY_SAVE - backup_top,
-				(void *)(CONFIG_RAMTOP - backup_top), backup_top);
-	}
-	memset_((void *)(CONFIG_RAMTOP - backup_top), 0, backup_top);
-
-	print_car_debug(" Done\n");
-}
-
 static void prepare_ramstage_region(int s3resume)
 {
-	size_t backup_top = backup_size();
 	print_car_debug("Prepare ramstage memory region...");
 
 	if (s3resume) {
 		void *resume_backup_memory = acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
 		if (resume_backup_memory)
 			memcpy_(resume_backup_memory, (void *) CONFIG_RAMBASE,
-				HIGH_MEMORY_SAVE - backup_top);
-		memset_((void*) CONFIG_RAMBASE, 0, HIGH_MEMORY_SAVE - backup_top);
+				HIGH_MEMORY_SAVE);
+		memset_((void*) CONFIG_RAMBASE, 0, HIGH_MEMORY_SAVE);
 	} else {
-		memset_((void*)0, 0, CONFIG_RAMTOP - backup_top);
+		memset_((void*)0, 0, CONFIG_RAMTOP);
 	}
 
 	print_car_debug(" Done\n");
@@ -111,6 +89,8 @@ static void vErrata343(void)
 	wrmsr(BU_CFG2_MSR, msr);
 }
 
+#define ROMSTAGE_RAM_STACK_SIZE 0x5000
+
 void post_cache_as_ram(void)
 {
 	uint32_t family = amd_fam1x_cpu_family();
@@ -128,7 +108,10 @@ void post_cache_as_ram(void)
 	if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) || s3resume)
 		cbmem_recovery(s3resume);
 
-	prepare_romstage_ramstack(s3resume);
+	/* FIXME: CBMEM stack is not wb-cacheable yet. */
+	uintptr_t ramtop = romstage_ram_stack_base(ROMSTAGE_RAM_STACK_SIZE,
+		s3resume ? ROMSTAGE_STACK_CBMEM : ROMSTAGE_STACK_LOW_MEM);
+	ramtop += ROMSTAGE_RAM_STACK_SIZE;
 
 	if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) {
 		struct romstage_handoff *handoff;
@@ -146,7 +129,7 @@ void post_cache_as_ram(void)
 	}
 
 	size_t car_size = car_data_size();
-	void *migrated_car = (void *)(CONFIG_RAMTOP - car_size);
+	void *migrated_car = (void *)(ramtop - car_size);
 
 	print_car_debug("Copying data from cache to RAM...");
 	memcpy_(migrated_car, _car_relocatable_data_start, car_size);