[coreboot-gerrit] Patch set updated for coreboot: google/reef: Add GPE routing settings

[Shaunak Saha (shaunak.saha@intel.com)]

Shaunak Saha (shaunak.saha at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15556

-gerrit

commit f4a7ab1a741e56b357de6b20c43e96a7a62bce17
Author: Shaunak Saha <shaunak.saha at intel.com>
Date:   Wed Jul 6 15:50:48 2016 -0700

    google/reef: Add GPE routing settings
    
    This patch sets the devicetree for gpe0_dw configuration
    and also confgigures the GPIO lines for SCI.EC_SCI_GPI
    is configured to proper value.
    
    BUG = chrome-os-partner:53438
    TEST = Toggle pch_sci_l from ec console using gpioset command
           and see that the sci counter increases in /sys/firmware/acpi/interrupt
           and also 9 in /proc/interrupt
    
    Change-Id: If258bece12768edb1e612c982514ce95c756c438
    Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
---
 src/mainboard/google/reef/devicetree.cb | 9 +++++++++
 src/mainboard/google/reef/ec.h          | 8 +++++---
 src/mainboard/google/reef/gpio.h        | 2 +-
 3 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb
index e0831f4..7f6d189 100644
--- a/src/mainboard/google/reef/devicetree.cb
+++ b/src/mainboard/google/reef/devicetree.cb
@@ -36,6 +36,15 @@ chip soc/intel/apollolake
 	# 0x1C[6:0] stands for 28*125 =  3500 pSec delay for HS200
 	register "emmc_rx_cmd_data_cntl2" = "0x1001C"
 
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route, i.e., If this route changes then the affected GPE
+	# offset bits also needs to be changed. This sets the PMC register
+	# GPE_CFG fields.
+	register "gpe0_dw1" = "PMC_GPE_N_31_0"
+	register "gpe0_dw2" = "PMC_GPE_N_63_32"
+	register "gpe0_dw3" = "PMC_GPE_SW_31_0"
+
 	device domain 0 on
 		device pci 00.0 on  end	# - Host Bridge
 		device pci 00.1 on  end	# - DPTF
diff --git a/src/mainboard/google/reef/ec.h b/src/mainboard/google/reef/ec.h
index 5a32697..3619c04 100644
--- a/src/mainboard/google/reef/ec.h
+++ b/src/mainboard/google/reef/ec.h
@@ -18,9 +18,11 @@
 
 #include <ec/google/chromeec/ec_commands.h>
 
-/* This is the GPE status bit.
-   TODO: Fix this to proper bit matching GPE routing table */
-#define EC_SCI_GPI   15
+/*
+ * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
+ * which is North community
+ */
+#define EC_SCI_GPI	GPE0_DW1_11
 
 #define MAINBOARD_EC_SCI_EVENTS \
 	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h
index 91e8bb1..eddefeb 100644
--- a/src/mainboard/google/reef/gpio.h
+++ b/src/mainboard/google/reef/gpio.h
@@ -283,7 +283,7 @@ static const struct pad_config gpio_table[] = {
 
 	PAD_CFG_GPI_APIC(GPIO_9, NONE, DEEP, LEVEL, NONE), /* dTPM IRQ */
 	PAD_CFG_GPI(GPIO_10, UP_20K, DEEP),	 /* unused */
-	PAD_CFG_GPI_SCI(GPIO_11, NONE, DEEP, LEVEL, NONE), /* EC SCI  */
+	PAD_CFG_GPI_SCI(GPIO_11, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC SCI  */
 	PAD_CFG_GPI(GPIO_12, UP_20K, DEEP),	 /* unused */
 	PAD_CFG_GPI(GPIO_13, UP_20K, DEEP),	 /* unused */
 	PAD_CFG_GPI_APIC(GPIO_14, UP_20K, DEEP, LEVEL, NONE), /* FP IRQ */