[coreboot-gerrit] Patch set updated for coreboot: mainboard/google/reef: add board_id() support

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15561

-gerrit

commit 42f973b071c84bbfa71e816ff88b8a1ffca25e4d
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Jul 6 22:53:51 2016 -0500

    mainboard/google/reef: add board_id() support
    
    The board build version is provided by the EC on reef.
    Provide the necessary functional support for coreboot
    to differentiate the board versions.
    
    BUG=chrome-os-partner:54960,chrome-os-partner:54961
    BRANCH=None
    TEST=Built and tested on reef.
    
    Change-Id: I1b7e8b2f4142753cde736148ca9495bcc625f318
    Signed-off-by: Aaron Durbin <adurbin at chromuim.org>
---
 src/mainboard/google/reef/Makefile.inc |  2 ++
 src/mainboard/google/reef/boardid.c    | 28 ++++++++++++++++++++++++++++
 src/mainboard/google/reef/gpio.h       |  8 ++++----
 3 files changed, 34 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/google/reef/Makefile.inc b/src/mainboard/google/reef/Makefile.inc
index f8fbbf3..6db0f2f 100644
--- a/src/mainboard/google/reef/Makefile.inc
+++ b/src/mainboard/google/reef/Makefile.inc
@@ -2,7 +2,9 @@ bootblock-y += bootblock.c
 bootblock-y += ec.c
 
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
+romstage-y += boardid.c
 
+ramstage-y += boardid.c
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-y += ec.c
 ramstage-y += mainboard.c
diff --git a/src/mainboard/google/reef/boardid.c b/src/mainboard/google/reef/boardid.c
new file mode 100644
index 0000000..4eb9f48
--- /dev/null
+++ b/src/mainboard/google/reef/boardid.c
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <boardid.h>
+#include <ec/google/chromeec/ec.h>
+
+uint8_t board_id(void)
+{
+	MAYBE_STATIC int id = -1;
+
+	if (id < 0)
+		id = google_chromeec_get_board_version();
+
+	return id;
+}
diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h
index d541a34..14cf880c 100644
--- a/src/mainboard/google/reef/gpio.h
+++ b/src/mainboard/google/reef/gpio.h
@@ -243,8 +243,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPIO_98, UP_20K, DEEP),	 /* FST_SPI_CS1_B -- unused */
 	PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1),	 /* FST_SPI_MOSI_IO0 */
 	PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1), /* FST_SPI_MISO_IO1 */
-	PAD_CFG_GPI(GPIO_101, UP_20K, DEEP),	 /* FST_IO2 -- unused */
-	PAD_CFG_GPI(GPIO_102, UP_20K, DEEP),	 /* FST_IO3 -- unused */
+	PAD_CFG_GPI(GPIO_101, UP_20K, DEEP),	 /* FST_IO2 -- MEM_CONFIG0 */
+	PAD_CFG_GPI(GPIO_102, UP_20K, DEEP),	 /* FST_IO3 -- MEM_CONFIG1 */
 	PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1), /* FST_SPI_CLK */
 
 	/* SIO_SPI_0 - Used for FP */
@@ -312,7 +312,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPIO_37, UP_20K, DEEP),	 /* unused */
 
 	/* LPSS_UART[0:2] */
-	PAD_CFG_GPI(GPIO_38, UP_20K, DEEP),	 /* LPSS_UART0_RXD - unused */
+	PAD_CFG_GPI(GPIO_38, UP_20K, DEEP),	 /* LPSS_UART0_RXD - MEM_CONFIG2*/
 	/* Next 2 are straps. */
 	PAD_CFG_GPI(GPIO_39, DN_20K, DEEP),	 /* LPSS_UART0_TXD - unused */
 	PAD_CFG_GPI(GPIO_40, DN_20K, DEEP),	 /* LPSS_UART0_RTS - unused */
@@ -320,7 +320,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1),	 /* LPSS_UART1_RXD */
 	PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1),	 /* LPSS_UART1_TXD */
 	PAD_CFG_NF(GPIO_44, NATIVE, DEEP, NF1),	 /* LPSS_UART1_RTS */
-	PAD_CFG_NF(GPIO_45, NATIVE, DEEP, NF1),	 /* LPSS_UART1_CTS */
+	PAD_CFG_GPI(GPIO_45, UP_20K, DEEP),	 /* LPSS_UART1_CTS - MEM_CONFIG3 */
 	PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1),	 /* LPSS_UART2_RXD */
 	PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1),	 /* LPSS_UART2_TXD */
 	PAD_CFG_GPI(GPIO_48, UP_20K, DEEP),	 /* LPSS_UART2_RTS - unused */