[coreboot-gerrit] Patch set updated for coreboot: pcengines/apu2: Add IVRS table generation

[Philipp Deppenwiese (zaolin.daisuki@googlemail.com)]

Philipp Deppenwiese (zaolin.daisuki at googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15165

-gerrit

commit 01e195dd0a603c77fa5ffa03fe63168e5667b42b
Author: Timothy Pearson <tpearson at raptorengineering.com>
Date:   Mon Jun 13 13:49:36 2016 -0500

    pcengines/apu2: Add IVRS table generation
    
    The resultant IVRS tables have been tested and work with
    PCI passthrough under Xen.
    
    Change-Id: I81b5b421098f29163d6ae98527de152c8046b1d9
    Signed-off-by: Timothy Pearson <tpearson at raptorengineering.com>
---
 src/mainboard/pcengines/apu2/acpi_tables.c | 35 +++++++++++++++++++++++++++---
 src/mainboard/pcengines/apu2/devicetree.cb |  2 +-
 2 files changed, 33 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/pcengines/apu2/acpi_tables.c b/src/mainboard/pcengines/apu2/acpi_tables.c
index 17995ce..c3e24c9 100644
--- a/src/mainboard/pcengines/apu2/acpi_tables.c
+++ b/src/mainboard/pcengines/apu2/acpi_tables.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Raptor Engineering, LLC
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -57,9 +58,37 @@ unsigned long acpi_fill_madt(unsigned long current)
 
 unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current)
 {
-	/* TODO
-	 * Add IVRS entries
-	 */
+	uint8_t *p;
+
+	uint32_t apicid_sb800;
+	uint32_t apicid_northbridge;
+
+	apicid_sb800 = CONFIG_MAX_CPUS;
+	apicid_northbridge = CONFIG_MAX_CPUS + 1;
+
+	/* Describe NB IOAPIC */
+	p = (uint8_t *)current;
+	p[0] = 0x48;                    /* Entry type */
+	p[1] = 0;                       /* Device */
+	p[2] = 0;                       /* Bus */
+	p[3] = 0x0;                     /* Data */
+	p[4] = apicid_northbridge;      /* IOAPIC ID */
+	p[5] = 0x0;                     /* Device 0 Function 0 */
+	p[6] = 0x0;                     /* Northbridge bus */
+	p[7] = 0x1;                     /* Variety */
+	current += 8;
+
+	/* Describe SB IOAPIC */
+	p = (uint8_t *)current;
+	p[0] = 0x48;                    /* Entry type */
+	p[1] = 0;                       /* Device */
+	p[2] = 0;                       /* Bus */
+	p[3] = 0xd7;                    /* Data */
+	p[4] = apicid_sb800;            /* IOAPIC ID */
+	p[5] = 0x14 << 3;               /* Device 0x14 Function 0 */
+	p[6] = 0x0;                     /* Southbridge bus */
+	p[7] = 0x1;                     /* Variety */
+	current += 8;
 
 	return current;
 }
diff --git a/src/mainboard/pcengines/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/devicetree.cb
index 3c5ec81..f402167 100644
--- a/src/mainboard/pcengines/apu2/devicetree.cb
+++ b/src/mainboard/pcengines/apu2/devicetree.cb
@@ -25,7 +25,7 @@ chip northbridge/amd/pi/00730F01/root_complex
 
 			chip northbridge/amd/pi/00730F01 # PCI side of HT root complex
 				device pci 0.0 on  end # Root Complex
-				device pci 0.2 off end # IOMMU
+				device pci 0.2 on end # IOMMU
 				device pci 1.0 off  end # Internal Graphics P2P bridge 0x9804
 				device pci 1.1 off  end # Internal Multimedia
 				device pci 2.0 on  end # PCIe Host Bridge