[coreboot-gerrit] Patch set updated for coreboot: nb/amd/pi/00730F01: Initialize IOMMU device
Philipp Deppenwiese (zaolin.daisuki@googlemail.com)
gerrit at coreboot.org
Tue Jul 5 17:00:41 CEST 2016
Philipp Deppenwiese (zaolin.daisuki at googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15186
-gerrit
commit 5f0d6112cf1f40254767614c9f787a08cb90fc1c
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Tue Jun 14 14:49:07 2016 -0500
nb/amd/pi/00730F01: Initialize IOMMU device
Change-Id: I12d3ed35770ee06626f884db23004652084c88c0
---
src/cpu/amd/pi/heapmanager.c | 4 +-
src/include/device/pci_ids.h | 1 +
src/northbridge/amd/pi/00730F01/Makefile.inc | 1 +
src/northbridge/amd/pi/00730F01/iommu.c | 71 ++++++++++++++++++++++++++++
src/northbridge/amd/pi/agesawrapper.c | 2 +
5 files changed, 77 insertions(+), 2 deletions(-)
diff --git a/src/cpu/amd/pi/heapmanager.c b/src/cpu/amd/pi/heapmanager.c
index c5e4202..f4e4492 100644
--- a/src/cpu/amd/pi/heapmanager.c
+++ b/src/cpu/amd/pi/heapmanager.c
@@ -41,7 +41,7 @@ void EmptyHeap(void)
memset(BiosManagerPtr, 0, BIOS_HEAP_SIZE);
}
-#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) && !defined(__PRE_RAM__)
+#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) && !defined(__PRE_RAM__)
#define AGESA_RUNTIME_SIZE 4096
@@ -87,7 +87,7 @@ AGESA_STATUS agesa_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr);
AllocParams->BufferPointer = NULL;
-#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) && !defined(__PRE_RAM__)
+#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) && !defined(__PRE_RAM__)
/* if the allocation is for runtime use simple CBMEM data */
if (Data == HEAP_CALLOUT_RUNTIME)
return alloc_cbmem(AllocParams);
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 72f1ece..f3e48ee 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -293,6 +293,7 @@
#define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200
#define PCI_DEVICE_ID_AMD_15H_NB_IOMMU 0x1419
#define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU 0x1423
+#define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_IOMMU 0x1567
#define PCI_DEVICE_ID_ATI_SB600_LPC 0x438D
#define PCI_DEVICE_ID_ATI_SB600_SATA 0x4380
diff --git a/src/northbridge/amd/pi/00730F01/Makefile.inc b/src/northbridge/amd/pi/00730F01/Makefile.inc
index 3cf4ed1..39c3ee6 100644
--- a/src/northbridge/amd/pi/00730F01/Makefile.inc
+++ b/src/northbridge/amd/pi/00730F01/Makefile.inc
@@ -16,3 +16,4 @@
romstage-y += dimmSpd.c
ramstage-y += northbridge.c
+ramstage-y += iommu.c
diff --git a/src/northbridge/amd/pi/00730F01/iommu.c b/src/northbridge/amd/pi/00730F01/iommu.c
new file mode 100644
index 0000000..00b65a4
--- /dev/null
+++ b/src/northbridge/amd/pi/00730F01/iommu.c
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <lib.h>
+
+static void iommu_read_resources(struct device *dev)
+{
+ struct resource *res;
+
+ /* Get the normal pci resources of this device */
+ pci_dev_read_resources(dev);
+
+ /* Add an extra subtractive resource for both memory and I/O. */
+ res = new_resource(dev, 0x44);
+ res->size = 512 * 1024;
+ res->align = log2(res->size);
+ res->gran = log2(res->size);
+ res->limit = 0xffffffff; /* 4G */
+ res->flags = IORESOURCE_MEM;
+}
+
+static void iommu_set_resources(struct device *dev)
+{
+ pci_dev_set_resources(dev);
+
+#if 0
+ struct resource *res;
+
+ res = find_resource(dev, 0x44);
+ /* Remember this resource has been stored */
+ res->flags |= IORESOURCE_STORED;
+ /* For now, do only 32-bit space allocation */
+ pci_write_config32(dev, 0x48, 0x0);
+ pci_write_config32(dev, 0x44, res->base | (1 << 0));
+#endif
+}
+
+static struct pci_operations lops_pci = {
+ .set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations iommu_ops = {
+ .read_resources = iommu_read_resources,
+ .set_resources = iommu_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = 0,
+ .scan_bus = 0,
+ .ops_pci = &lops_pci,
+};
+
+static const struct pci_driver iommu_driver __pci_driver = {
+ .ops = &iommu_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_IOMMU,
+};
diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c
index b1e514a..c345f68 100644
--- a/src/northbridge/amd/pi/agesawrapper.c
+++ b/src/northbridge/amd/pi/agesawrapper.c
@@ -299,6 +299,8 @@ AGESA_STATUS agesawrapper_amdinitlate(void)
/* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */
AmdCreateStruct(&AmdParamStruct);
AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr;
+ AmdLateParams->GnbLateConfiguration.GnbIoapicId = 0x05;
+ AmdLateParams->GnbLateConfiguration.FchIoapicId = 0x04;
Status = AmdInitLate(AmdLateParams);
if (Status != AGESA_SUCCESS) {
agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus);
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