[coreboot-gerrit] Patch set updated for coreboot: SPD: Add CAS latency 2

[HAOUAS Elyes (ehaouas@noos.fr)]

HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15439

-gerrit

commit 3282424ceba6c2db6a6e6fec0f4b1157c6fff3c6
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date:   Sun Jun 26 17:46:21 2016 +0200

    SPD: Add CAS latency 2
    
    CAS latency = 2 support added for DDR2.
    
    Change-Id: I08d72a61c27ff0eab19e500a2f547a5e946de2f0
    Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
 src/include/spd.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/include/spd.h b/src/include/spd.h
index 6424d33..0bc7898 100644
--- a/src/include/spd.h
+++ b/src/include/spd.h
@@ -147,6 +147,7 @@ enum spd_memory_type {
 #define SPD_CAS_LATENCY_3_5              0x20
 #define SPD_CAS_LATENCY_4_0              0x40
 
+#define SPD_CAS_LATENCY_DDR2_2		(1 << 2)
 #define SPD_CAS_LATENCY_DDR2_3		(1 << 3)
 #define SPD_CAS_LATENCY_DDR2_4		(1 << 4)
 #define SPD_CAS_LATENCY_DDR2_5		(1 << 5)