[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/apollolake: Add support for LPSS I2C driver

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit ff8bce0a5f53652d4d26cb501159e8711f79eb9b
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Jun 27 10:57:13 2016 -0700

    soc/intel/apollolake: Add support for LPSS I2C driver
    
    Support the I2C interfaces on this SOC using the Intel common lpss_i2c
    driver.  The controllers are supported in pre-ram environments by
    setting a temporary base address in bootblock and in ramstage using
    the naturally enumerated base address.
    
    The base speed of this controller is 133MHz and the SCL/SDA timing
    values that are reported to the OS are calculated using that clock.
    
    This was tested on a google/reef board doing I2C transactions to the
    trackpad both in verstage and in ramstage.
    
    Change-Id: I0a9d62cd1007caa95cdf4754f30c30aaff9f78f9
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://review.coreboot.org/15480
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/15480 for details.

-gerrit