[coreboot-gerrit] Patch set updated for coreboot: google/reef: Add Maxim98357a support
HARSHAPRIYA N (harshapriya.n@intel.com)
gerrit at coreboot.org
Sat Jul 2 01:10:38 CEST 2016
HARSHAPRIYA N (harshapriya.n at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15435
-gerrit
commit 27833159890c1574ec66a1e9015b0ea88cdbb29d
Author: Harsha Priya <harshapriya.n at intel.com>
Date: Fri Jun 24 17:13:54 2016 -0700
google/reef: Add Maxim98357a support
Adds Maxim98357a support for reef using the generic driver
in drivers/generic/max98357
Change-Id: I333d4e810e42309ac76dd90c19f05cf3e3a517e0
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella at intel.com>
---
src/mainboard/google/reef/Kconfig | 3 +++
src/mainboard/google/reef/devicetree.cb | 7 ++++++-
src/soc/intel/apollolake/chip.h | 2 ++
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig
index ded75bb..489b0b6 100644
--- a/src/mainboard/google/reef/Kconfig
+++ b/src/mainboard/google/reef/Kconfig
@@ -51,4 +51,7 @@ config INCLUDE_NHLT_BLOBS
select NHLT_DA7219
select NHLT_MAX98357
+config DRIVERS_GENERIC_MAX98357A
+ default y
+
endif # BOARD_GOOGLE_REEF
diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb
index d2b295f..93f9ae5 100644
--- a/src/mainboard/google/reef/devicetree.cb
+++ b/src/mainboard/google/reef/devicetree.cb
@@ -46,7 +46,12 @@ chip soc/intel/apollolake
device pci 0d.1 on end # - PMC
device pci 0d.2 on end # - SPI
device pci 0d.3 on end # - Shared SRAM
- device pci 0e.0 on end # - Audio
+ device pci 0e.0 on # - Audio
+ chip drivers/generic/max98357a
+ register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPIO_76)"
+ device generic 0 on end
+ end
+ end
device pci 11.0 on end # - ISH
device pci 12.0 off end # - SATA
device pci 13.0 off end # - Root Port 2 - PCIe-A 0
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index ef82c53..ce15f6d 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -18,6 +18,8 @@
#ifndef _SOC_APOLLOLAKE_CHIP_H_
#define _SOC_APOLLOLAKE_CHIP_H_
+#include <soc/gpio_defs.h>
+
#define CLKREQ_DISABLED 0xf
/* Serial IRQ control. SERIRQ_QUIET is the default (0). */
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