[coreboot-gerrit] New patch to review for coreboot: reef: Enable I2C TPM

[Duncan Laurie (dlaurie@chromium.org)]

Duncan Laurie (dlaurie at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15527

-gerrit

commit c8c8ed3c150f56a9b863805df70fe11664dc4176
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Jun 30 14:50:04 2016 -0700

    reef: Enable I2C TPM
    
    Enable I2C bus 2 for TPM at address 0x50.  This is needed in
    verstage so enable the pads and the I2C controller early.
    
    Change-Id: Ib696ace0274344ae3f527d883f56fae59dc41590
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/mainboard/google/reef/Kconfig       | 9 +++++++++
 src/mainboard/google/reef/devicetree.cb | 3 +++
 src/mainboard/google/reef/gpio.h        | 3 +++
 3 files changed, 15 insertions(+)

diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig
index 194a6ba..603866a 100644
--- a/src/mainboard/google/reef/Kconfig
+++ b/src/mainboard/google/reef/Kconfig
@@ -28,6 +28,15 @@ config CHROMEOS
 config DRIVERS_I2C_GENERIC
 	default y
 
+config I2C_TPM
+	default y
+
+config DRIVER_TPM_I2C_ADDR
+	default 0x50
+
+config DRIVER_TPM_I2C_BUS
+	default 0x2
+
 config MAINBOARD_DIR
 	string
 	default google/reef
diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb
index e0831f4..f18caa8 100644
--- a/src/mainboard/google/reef/devicetree.cb
+++ b/src/mainboard/google/reef/devicetree.cb
@@ -36,6 +36,9 @@ chip soc/intel/apollolake
 	# 0x1C[6:0] stands for 28*125 =  3500 pSec delay for HS200
 	register "emmc_rx_cmd_data_cntl2" = "0x1001C"
 
+	# I2C bus for TPM needed in verstage
+	register "i2c[2].early_init" = "1"
+
 	device domain 0 on
 		device pci 00.0 on  end	# - Host Bridge
 		device pci 00.1 on  end	# - DPTF
diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h
index bd491b4..d95d11b 100644
--- a/src/mainboard/google/reef/gpio.h
+++ b/src/mainboard/google/reef/gpio.h
@@ -341,6 +341,9 @@ static const struct pad_config gpio_table[] = {
 /* GPIOs needed prior to ramstage. */
 static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_GPI(GPIO_75, UP_20K, DEEP),	 /* I2S1_BCLK -- PCH_WP */
+	/* I2C2 - TPM  */
+	PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1),	 /* LPSS_I2C2_SDA */
+	PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1),	 /* LPSS_I2C2_SCL */
 };
 
 #endif /* __ACPI__ */