[coreboot-gerrit] Patch merged into coreboot/master: skylake: Generate ACPI timing values for I2C devices

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 222381e390191d7a4476642ae0e544c96349a096
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Jun 21 10:41:19 2016 -0700

    skylake: Generate ACPI timing values for I2C devices
    
    Have the Skylake SOC generate ACPI timing values for the enabled I2C
    controllers instead of passing it in the DSDT with static timings.
    
    The timing values are generated from the controller clock speed and
    are more accurate than the hardcoded values that were in the ASL which
    were originally copied from Broadwell where the controller is running
    at a different clock speed...
    
    Additionally it is now possible for a board to override the values
    using devicetree.cb.  If zero is passed in for SCL HCNT or LCNT then
    the kernel will generate its own timing using the same forumla, but if
    the SDA hold time value is zero the kernel will NOT generate a correct
    value and the SDA hold time may be incorrect.
    
    This was tested on the Chell platform to ensure all the I2C devices on
    the board are still operational with these new timing values.
    
    Change-Id: I4feb3df9e083592792f8fadd7105e081a984a906
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://review.coreboot.org/15291
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/15291 for details.

-gerrit