[coreboot-gerrit] Patch set updated for coreboot: arch/riscv: Change all eret instructions to mret
Jonathan Neuschäfer (j.neuschaefer@gmx.net)
gerrit at coreboot.org
Fri Jul 1 00:22:21 CEST 2016
Jonathan Neuschäfer (j.neuschaefer at gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15290
-gerrit
commit 452714cdd4ad31158beb1f46365a36b365eae3bd
Author: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Date: Thu Jun 30 22:58:53 2016 +0200
arch/riscv: Change all eret instructions to mret
Change-Id: I17e14d4793ae5259f7ce3ce0211cbb27305506cc
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
---
src/arch/riscv/boot.c | 2 +-
src/arch/riscv/trap_util.S | 4 ++--
src/arch/riscv/virtual_memory.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c
index 5830ac4..01bb0ac 100644
--- a/src/arch/riscv/boot.c
+++ b/src/arch/riscv/boot.c
@@ -26,7 +26,7 @@ void arch_prog_run(struct prog *prog)
if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) {
initVirtualMemory();
write_csr(mepc, doit);
- asm volatile("eret");
+ asm volatile("mret");
} else {
doit(prog_entry_arg(prog));
}
diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S
index 0118ffc..6608328 100644
--- a/src/arch/riscv/trap_util.S
+++ b/src/arch/riscv/trap_util.S
@@ -124,9 +124,9 @@ trap_entry:
supervisor_call_return:
csrr a0, mscratch
restore_regs
- eret # go back into supervisor call
+ mret # go back into supervisor call
.global machine_call_return
machine_call_return:
csrr a0, mscratch
restore_regs
- eret # go back into machine call
+ mret # go back into machine call
diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index dce0887..3edd5cf 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -31,7 +31,7 @@ void walk_page_table(void) {
void enter_supervisor(void) {
// enter supervisor mode
- asm volatile("la t0, 1f; csrw mepc, t0; eret; 1:" ::: "t0");
+ asm volatile("la t0, 1f; csrw mepc, t0; mret; 1:" ::: "t0");
}
void flush_tlb(void)
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