[coreboot-gerrit] New patch to review for coreboot: src/: Fix Kcofig symbols missing CONFIG_ prefix

[Martin Roth (martinroth@google.com)]

Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13539

-gerrit

commit d0fd71c1be6c56e3bf0cd9a812c72ffc4d20a662
Author: Martin Roth <martinroth at google.com>
Date:   Sun Jan 31 10:37:22 2016 -0700

    src/: Fix Kcofig symbols missing CONFIG_ prefix
    
    - Add CONFIG_ prefix to two symbols.
    - Remove the use of the third symbol as it will never be matched.
    
    Change-Id: Ifa7f6884001cb05fb8397f193c4b08a0161f498c
    Signed-off-by: Martin Roth <martinroth at google.com>
---
 src/cpu/amd/car/disable_cache_as_ram.c       | 2 +-
 src/mainboard/intel/bayleybay_fsp/romstage.c | 2 +-
 src/mainboard/siemens/mc_tcu3/romstage.c     | 4 ----
 3 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c
index e8d5af8..1eb3dd7 100644
--- a/src/cpu/amd/car/disable_cache_as_ram.c
+++ b/src/cpu/amd/car/disable_cache_as_ram.c
@@ -72,7 +72,7 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(uint8_t s
 
 	family = amd_fam1x_cpu_family();
 
-#if IS_ENABLED(CPU_AMD_MODEL_10XXX)
+#if IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)
 	if (family >= 0x6f) {
 		/* Family 15h or later */
 
diff --git a/src/mainboard/intel/bayleybay_fsp/romstage.c b/src/mainboard/intel/bayleybay_fsp/romstage.c
index 7af782f..56ca33a 100644
--- a/src/mainboard/intel/bayleybay_fsp/romstage.c
+++ b/src/mainboard/intel/bayleybay_fsp/romstage.c
@@ -171,7 +171,7 @@ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
 	UpdData->AzaliaConfigPtr  = (UINT32)&mainboard_AzaliaConfig;
 
 	/* Disable 2nd DIMM on Bakersport*/
-#if IS_ENABLED(BOARD_INTEL_BAKERSPORT_FSP)
+#if IS_ENABLED(CONFIG_BOARD_INTEL_BAKERSPORT_FSP)
 	UpdData->PcdMrcInitSPDAddr2 = 0x00; /* cannot use SPD_ADDR_DISABLED at this point */
 #endif
 }
diff --git a/src/mainboard/siemens/mc_tcu3/romstage.c b/src/mainboard/siemens/mc_tcu3/romstage.c
index 49483e5..1fa78ca 100644
--- a/src/mainboard/siemens/mc_tcu3/romstage.c
+++ b/src/mainboard/siemens/mc_tcu3/romstage.c
@@ -172,10 +172,6 @@ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
 	/* Initialize the Azalia Verb Tables to mainboard specific version */
 	UpdData->AzaliaConfigPtr  = (UINT32)&mainboard_AzaliaConfig;
 
-	/* Disable 2nd DIMM on Bakersport*/
-#if IS_ENABLED(BOARD_INTEL_BAKERSPORT_FSP)
-	UpdData->PcdMrcInitSPDAddr2 = 0x00; /* cannot use SPD_ADDR_DISABLED at this point */
-#endif
 	/* Get SPD data from hardware information block and setup memory down */
 	/* parameters for FSP accordingly */
 	hwi_main = get_hwinfo((char*)"hwinfo.hex");