[coreboot-gerrit] Patch set updated for coreboot: Documentation: Add x86 bootblock support
Leroy P Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Sun Jan 31 04:02:49 CET 2016
Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13441
-gerrit
commit c4d39336c4cae9e1266deb5c9bc13505cfdd0ba1
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Sat Jan 30 17:32:00 2016 -0800
Documentation: Add x86 bootblock support
Document what is involved with adding the bootblock support.
TEST=None
Change-Id: I6c8cc38e1b9346b4962588b33ca5e4ab8eac24c3
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
Documentation/Intel/SoC/soc.html | 96 ++++++++++++++++++++++++++++++++++++
Documentation/Intel/development.html | 1 +
2 files changed, 97 insertions(+)
diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html
index ffa4a04..3fb61f6 100644
--- a/Documentation/Intel/SoC/soc.html
+++ b/Documentation/Intel/SoC/soc.html
@@ -17,6 +17,7 @@
<li>SoC <a href="#RequiredFiles">Required Files</a></li>
<li><a href="#Descriptor">Start Booting</a></li>
<li><a href="#EarlyDebug">Early Debug</a></li>
+ <li><a href="#Bootblock">Bootblock</a></li>
</ol>
@@ -100,6 +101,101 @@ mv build/coreboot.rom.new build/coreboot.rom
<hr>
+<h1><a name="Bootblock">Bootblock</a></h1>
+<p>
+ Implement the bootblock using the following steps:
+</p>
+<ol>
+ <li>Create the directory as src/soc/<Vendor>/<Chip Family>/bootblock</li>
+ <li>Add the timestamp.inc file which initializes the floating point registers and saves
+ the initial timestamp.
+ </li>
+ <li>Add the bootblock.c file which:
+ <ol type="A">
+ <li>Enables memory-mapped PCI config access</li>
+ <li>Updates the microcode by calling intel_update_microcode_from_cbfs</li>
+ <li>Enable ROM caching</li>
+ </ol>
+ </li>
+ <li>Edit the src/soc/<Vendor>/<Chip Family>/Kconfig file
+ <ol type="A">
+ <li>Add the BOOTBLOCK_CPU_INIT value to point to the bootblock.c file</li>
+ <li>Add the CHIPSET_BOOTBLOCK_INCLUDE value to point to the timestamp.inc file</li>
+ </ol>
+ </li>
+ <li>Edit the src/soc/<Vendor>/<Chip Family>/Makefile.inc file
+ <ol type="A">
+ <li>Add the bootblock subdirectory</li>
+ </ol>
+ </li>
+ <li>Edit the src/soc/<Vendor>/<Chip Family>/memmap.c file
+ <ol type="A">
+ <li>Add the fsp/memmap.h include file</li>
+ <li>Add the mmap_region_granularity routine</li>
+ </ol>
+ </li>
+ <li>Add the necessary .h files to define the necessary values and structures</li>
+ <li>When successful port 0x80 will output the following values:
+ <ol type="A">
+ <li>0x01: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l45">POST_RESET_VECTOR_CORRECT</a>
+ - Bootblock successfully executed the
+ <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc;hb=HEAD#l4">reset vector</a>
+ and entered the 16-bit code at
+ <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc;hb=HEAD#l35">_start</a>
+ </li>
+ <li>0x10: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l53">POST_ENTER_PROTECTED_MODE</a>
+ - Bootblock executing in
+ <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit/entry32.inc;hb=HEAD#l55">32-bit mode</a>
+ </li>
+ <li>0x10 - Verstage/romstage reached 32-bit mode</li>
+ </ol>
+ </li>
+</ol>
+
+<p>
+ <b>Build Note:</b> The following files are included into the default bootblock image:
+</p>
+<ul>
+ <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/bootblock_romcc.S;hb=HEAD">src/arch/x86/bootblock_romcc.S</a>
+ added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l133">src/arch/x86/Makefile.inc</a>
+ and includes the following files:
+ <ul>
+ <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/prologue.inc">src/arch/x86/prologue.inc</a></li>
+ <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc">src/cpu/x86/16bit/reset16.inc</a></li>
+ <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc">src/cpu/x86/16bit/entry16.inc</a></li>
+ <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit/entry32.inc">src/cpu/x86/32bit/entry32.inc</a></li>
+ <li>The code in
+ <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/bootblock_romcc.S">src/arch/x86/bootblock_romcc.S</a>
+ includes src/soc/<Vendor>/<Chip Family>/bootblock/timestamp.inc using the
+ CONFIG_CHIPSET_BOOTBLOCK_INCLUDE value set above
+ </li>
+ <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/sse_enable.inc">src/cpu/x86/sse_enable.inc</a></li>
+ <li>The code in
+ <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l156">src/arch/x86/Makefile.inc</a>
+ invokes the ROMCC tool to convert the following "C" code into assembler as bootblock.inc:
+ <ul>
+ <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/include/arch/bootblock_romcc.h">src/arch/x86/include/arch/bootblock_romcc.h</a></li>
+ <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/lapic/boot_cpu.c">src/cpu/x86/lapic/boot_cpu.c</a></li>
+ <li>The CONFIG_BOOTBLOCK_CPU_INIT value set above typically points to the code in
+ src/soc/<Vendor>/<Chip Family>/bootblock/bootblock.c
+ </li>
+ </ul>
+ </li>
+ </ul>
+ </li>
+ <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/id.S">src/arch/x86/id.S</a>
+ added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l110">src/arch/x86/Makefile.inc</a>
+ </li>
+ <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/fit.S">src/cpu/intel/fit/fit.S</a>
+ added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/Makefile.inc;hb=HEAD">src/cpu/intel/fit/Makefile.inc</a>
+ </li>
+ <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/walkcbfs.S">src/arch/x86/walkcbfs.S</a>
+ added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l137">src/arch/x86/Makefile.inc</a>
+ </li>
+</ul>
+
+
+<hr>
<p>Modified: 30 January 2016</p>
</body>
</html>
\ No newline at end of file
diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html
index 45477e0..7cb9b07 100644
--- a/Documentation/Intel/development.html
+++ b/Documentation/Intel/development.html
@@ -60,6 +60,7 @@
</li>
<li>Get result to start <a target="_blank" href="SoC/soc.html#Descriptor">booting</a></li>
<li><a target="_blank" href="SoC/soc.html#EarlyDebug">Early Debug</a></li>
+ <li>Implement and debug the <a target="_blank" href="SoC/soc.html#Bootblock">bootblock</a> code</li>
</ol>
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