[coreboot-gerrit] New patch to review for coreboot: soc/intel/common: Use SoC specific routine to read/write MTRRs
Leroy P Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Sun Jan 31 04:00:46 CET 2016
Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13529
-gerrit
commit 1e09578e8c0b7a656517e771e4f91b6913c18529
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Fri Jan 29 14:35:13 2016 -0800
soc/intel/common: Use SoC specific routine to read/write MTRRs
The registers associated with the MTRRs for Quark are referenced through
a port on the host bridge. Support the standard configurations by
providing a weak routines which just do a rdmsr/wrmsr.
Testing:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select DISPLAY_MTRRS"
* Add "select HAVE_FSP_PDAT_FILE"
* Add "select HAVE_FSP_RAW_BIN"
* Add "select HAVE_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if:
* The MTRRs are displayed and
* The message "FspTempRamExit returned successfully" is displayed
TEST=Build and run on Galileo
Change-Id: If2fea66d4b054be4555f5f172ea5945620648325
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
src/drivers/intel/fsp1_1/Kconfig | 7 +++++
src/drivers/intel/fsp1_1/after_raminit.S | 13 +++++++++
src/drivers/intel/fsp1_1/include/fsp/romstage.h | 2 ++
src/soc/intel/common/util.c | 37 ++++++++++++++++---------
src/soc/intel/common/util.h | 3 ++
5 files changed, 49 insertions(+), 13 deletions(-)
diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig
index 9b2c463..39c2f6b 100644
--- a/src/drivers/intel/fsp1_1/Kconfig
+++ b/src/drivers/intel/fsp1_1/Kconfig
@@ -103,6 +103,13 @@ config ROMSTAGE_RAM_STACK_SIZE
hex "Size of the romstage RAM stack in bytes"
default 0x5000
+config SOC_SETS_MTRRS
+ bool
+ default n
+ help
+ The SoC needs uses different access methods for reading and writing
+ the MTRRs. Use SoC specific routines to handle the MTRR access.
+
config USE_GENERIC_FSP_CAR_INC
bool
default n
diff --git a/src/drivers/intel/fsp1_1/after_raminit.S b/src/drivers/intel/fsp1_1/after_raminit.S
index eb99157..7486e33 100644
--- a/src/drivers/intel/fsp1_1/after_raminit.S
+++ b/src/drivers/intel/fsp1_1/after_raminit.S
@@ -87,6 +87,13 @@
* +0: Number of variable MTRRs to clear
*/
+#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS)
+ push %esp
+ call soc_set_mtrrs
+
+ /* Remove the parameters from the stack */
+ movl %eax, %esp
+#else
/* Clear all of the variable MTRRs. */
popl %ebx
movl $MTRR_PHYS_BASE(0), %ecx
@@ -129,6 +136,8 @@
dec %ebx
jmp 2b
2:
+#endif /* CONFIG_SOC_SETS_MTRRS */
+
post_code(0x39)
/* And enable cache again after setting MTRRs. */
@@ -138,11 +147,15 @@
post_code(0x3a)
+#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS)
+ call soc_enable_mtrrs
+#else
/* Enable MTRR. */
movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
orl $MTRR_DEF_TYPE_EN, %eax
wrmsr
+#endif /* CONFIG_SOC_SETS_MTRRS */
post_code(0x3b)
diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
index 4683f5e..b861eeb 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
@@ -87,5 +87,7 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
void soc_memory_init_params(struct romstage_params *params,
MEMORY_INIT_UPD *upd);
void soc_pre_ram_init(struct romstage_params *params);
+asmlinkage void *soc_set_mtrrs(uint32_t *top_of_stack);
+asmlinkage void soc_enable_mtrrs(void);
#endif /* _COMMON_ROMSTAGE_H_ */
diff --git a/src/soc/intel/common/util.c b/src/soc/intel/common/util.c
index dc3f139..64bf61f 100644
--- a/src/soc/intel/common/util.c
+++ b/src/soc/intel/common/util.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2015 Intel Corporation.
+ * Copyright (C) 2015-2016 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -15,22 +15,32 @@
#include <arch/cpu.h>
#include <console/console.h>
-#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <soc/intel/common/util.h>
#include <stddef.h>
+__attribute__((weak)) msr_t soc_mtrr_read(unsigned long index)
+{
+ return rdmsr(index);
+}
+
+__attribute__((weak)) void soc_mtrr_write(unsigned long index, msr_t msr)
+{
+ return wrmsr(index, msr);
+}
+
+
uint32_t soc_get_variable_mtrr_count(uint64_t *msr)
{
union {
uint64_t u64;
msr_t s;
- } mttrcap;
+ } mtrrcap;
- mttrcap.s = rdmsr(MTRR_CAP_MSR);
+ mtrrcap.s = soc_mtrr_read(MTRR_CAP_MSR);
if (msr != NULL)
- *msr = mttrcap.u64;
- return mttrcap.u64 & MTRR_CAP_VCNT;
+ *msr = mtrrcap.u64;
+ return mtrrcap.u64 & MTRR_CAP_VCNT;
}
static const char *soc_display_mtrr_type(uint32_t type)
@@ -84,7 +94,7 @@ static void soc_display_4k_mtrr(uint32_t msr_reg, uint32_t starting_address,
msr_t s;
} msr;
- msr.s = rdmsr(msr_reg);
+ msr.s = soc_mtrr_read(msr_reg);
printk(BIOS_DEBUG, "0x%016llx: %s\n", msr.u64, name);
soc_display_mtrr_fixed_types(msr.u64, starting_address, 0x1000);
}
@@ -97,7 +107,7 @@ static void soc_display_16k_mtrr(uint32_t msr_reg, uint32_t starting_address,
msr_t s;
} msr;
- msr.s = rdmsr(msr_reg);
+ msr.s = soc_mtrr_read(msr_reg);
printk(BIOS_DEBUG, "0x%016llx: %s\n", msr.u64, name);
soc_display_mtrr_fixed_types(msr.u64, starting_address, 0x4000);
}
@@ -109,7 +119,7 @@ static void soc_display_64k_mtrr(void)
msr_t s;
} msr;
- msr.s = rdmsr(MTRR_FIX_64K_00000);
+ msr.s = soc_mtrr_read(MTRR_FIX_64K_00000);
printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_FIX64K_00000\n", msr.u64);
soc_display_mtrr_fixed_types(msr.u64, 0, 0x10000);
}
@@ -137,12 +147,13 @@ static void soc_display_mtrr_def_type(void)
msr_t s;
} msr;
- msr.s = rdmsr(MTRR_DEF_TYPE_MSR);
+ msr.s = soc_mtrr_read(MTRR_DEF_TYPE_MSR);
printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_DEF_TYPE:%s%s %s\n",
msr.u64,
(msr.u64 & MTRR_DEF_TYPE_EN) ? " E," : "",
(msr.u64 & MTRR_DEF_TYPE_FIX_EN) ? " FE," : "",
- soc_display_mtrr_type((uint32_t)(msr.u64 & MTRR_DEF_TYPE_MASK)));
+ soc_display_mtrr_type((uint32_t)(msr.u64 &
+ MTRR_DEF_TYPE_MASK)));
}
static void soc_display_variable_mtrr(uint32_t msr_reg, int index,
@@ -160,8 +171,8 @@ static void soc_display_variable_mtrr(uint32_t msr_reg, int index,
msr_t s;
} msr_m;
- msr_a.s = rdmsr(msr_reg);
- msr_m.s = rdmsr(msr_reg + 1);
+ msr_a.s = soc_mtrr_read(msr_reg);
+ msr_m.s = soc_mtrr_read(msr_reg + 1);
if (msr_m.u64 & MTRR_PHYS_MASK_VALID) {
base_address = (msr_a.u64 & 0xfffffffffffff000ULL)
& address_mask;
diff --git a/src/soc/intel/common/util.h b/src/soc/intel/common/util.h
index 8c41151..1579e00 100644
--- a/src/soc/intel/common/util.h
+++ b/src/soc/intel/common/util.h
@@ -17,9 +17,12 @@
#define _INTEL_COMMON_UTIL_H_
#include <arch/cpu.h>
+#include <cpu/x86/msr.h>
#include <stdint.h>
asmlinkage void soc_display_mtrrs(void);
uint32_t soc_get_variable_mtrr_count(uint64_t *msr);
+msr_t soc_mtrr_read(unsigned long index);
+void soc_mtrr_write(unsigned long index, msr_t msr);
#endif /* _INTEL_COMMON_UTIL_H_ */
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